IBM has unveiled a sub-1nm chip technology, featuring a new transistor architecture at the 0.7nm or 7 angstrom node.

IBM’s chip technology is based on the company’s new “nanostack” transistor architecture. Nanostack is a 3D-like technology, which represents a new and different way to scale semiconductor devices in the future.

But don’t expect nanostack-based chips anytime soon. With the expectation of the earliest adoption of nanostack technology at the sub-1nm node, IBM sees a path to production in as early as the next five years.

Basically, a transistor is a key building block in a chip. Transistors are tiny structures used to amplify or switch electrical signals in the device. Today’s advanced chips integrate billions of tiny transistors in the same device.

Nonetheless, IBM’s nanostack technology makes use of 3D nanosheet-based design techniques. “The nanostack design vertically stacks and staggers transistors, taking advantage of 3D sequential integration to pack more transistors onto a chip. The design also unlocks the use of different material combinations within each stacked layer, optimizing performance and power efficiency of each transistor independent of the other,” according to IBM.

IBM’s new sub-1nm chip packs nearly 100 billion transistors onto a chip the size of a fingernail, nearly twice the density of IBM’s 2nm chip unveiled in 2021, according to Big Blue.

At the recent VLSI Symposium, IBM demonstrated that the nanostack architecture provides a 40% scaling benefit for SRAMs. In general, a 0.7nm nanostack chip provides up to 50% more performance, or 70% greater energy efficiency, than IBM’s 2nm node chips.

Potential applications for nanostack-based chips range from generative AI and cloud infrastructure to next-generation electronic devices. “IBM’s latest chip breakthrough marks a landmark moment in computing, pushing technology beyond the nanometer era to the scale of atoms. With our new nanostack architecture, we’re not just making smaller transistors, we’re reinventing how chips are built to deliver dramatically more power and energy efficiency,” said Jay Gambetta, director of IBM Research and IBM Fellow.

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Nanostack vs CFETs

Still, the question is clear: When will IBM’s nanostack technology appear in the market? To be sure, it won’t appear in the near term. It may never appear.

Today, leading-edge chipmakers, namely Intel, Samsung and TSMC, are manufacturing chips based on their new and respective 2nm process technologies. Today, 2nm represents the world’s most advanced process.

The new 2nm chips are based on a newfangled transistor architecture called gate-all-around (GAA). More specifically, chipmakers are ramping up a GAA technology called a nanosheet field-effect transistor (FET). Nanosheet technology was invented by IBM.

The nanosheet FET is expected to extend for at least three process generations, including the 2nm, A14 and A10 nodes. Then, at some point in the future, nanosheet FETs could run out of steam.

After the nanosheet FET, the complementary field-effect transistor (CFET) is the next leading logic transistor candidate on the roadmap (See Figure 1). In R&D, Intel, Samsung, TSMC and others are developing CFETs. Based on the roadmap, CFETs could appear at the A7 technology node in 2031.

Figure 1. The evolution of the transistor. Planar and finFET transistors are in production today. Nanosheets FETs are ramping up. CFETs are on the horizon. Source: Imec

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What about nanostack?

Meanwhile, for the same timeframe, IBM is developing another possible future transistor option for chips--nanostack technology. As stated, IBM sees a path towards production as early as the next five years.

In other words, CFETs and nanostack transistors could be viewed as competitive technologies. CFETs are different than nanostack technology. In CFETs, the NFET and PFET transistors are stacked on top of each other in a vertical fashion.

Nonetheless, the semiconductor industry doesn’t have the resources to develop both the CFET and nanostack technologies. Simply put, it’s too expensive.

So, the industry will eventually rally around one technology. Right now, CFETs have the most momentum, but the industry is always searching for a better solution.

If CFETs and nanostacks fail to make it into production in the future, the industry still has several backup options. Advanced packaging and chiplets may prevail in the long term.

Today, for leading-edge devices, chip vendors tend to integrate all functions on a large monolithic die. That’s becoming too expensive for some chip designs. In chiplets, the idea is to develop smaller dies with different functions. Then, the dies assembled into an advanced package. That’s fast becoming the main option for today’s advanced AI chip designs.

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For some time, the United States and China have been vying for the leadership position in several technical areas.

Those segments include AI, computing, communications, defense, robotics, self-driving cars, space exploration and others. The U.S. is leading in many areas, but China is gaining ground in others.

This should set off some alarm bells in the West: China is suddenly leading the supercomputer race.

Supercomputers are large and powerful general-purpose systems. They are the mainstream computing systems for today’s high-end applications. Supercomputers are used for various complex, number-crunching applications, such as defense/aerospace, math, physics, medical research, weather forecasting and others.

Nonetheless, the new LineShine supercomputer from China is ranked as the world’s most powerful supercomputer, displacing a U.S.-based system for the top spot, according to the new rankings from the TOP500 project. This marks the first time since 2017 that a Chinese supercomputer has led the TOP500 rankings.

LineShine, a previously unlisted system in the rankings, has displaced El Capitan as the world’s most powerful supercomputer as measured by the High Performance Linpack (HPL) benchmark, according to the rankings. The U.S.-based El Capitan supercomputer is located at the Lawrence Livermore National Laboratory in California.

LineShine achieved 2.198 Exaflop/s on HPL — about 80% of its 2.736 Exaflop/s theoretical peak — making it the first system on the TOP500 to exceed two exaflops of sustained double-precision performance using CPUs only. “An exaflop is a measure of performance for a supercomputer that can calculate at least one quintillion floating-point operations per second,” according to Nvidia.

Installed at the National Supercomputing Center in Shenzhen (NSCS) and built by the Shenzhen Cloud Computing Center, LineShine is based on a custom Chinese processor and the “LingKun” platform.

The system consists of 13.79 million cores across 304-core LX2 processors running at 1.55GHz, linked by the proprietary LingQi interconnect and running Kylin OS, according to the TOP500 project. LineShine draws 42.2 megawatts of power for an efficiency of 52.07 Gigaflops/Watt.

Meanwhile, the El Capitan supercomputer fell from first to second place in the rankings. As before, this supercomputer achieved 1.809 Exaflop/s of performance with 11.34 million cores. This system is based on HPE’s Cray EX255a architecture with AMD’s 4th Gen EPYC CPUs and Instinct MI300A accelerators.

Located at Oak Ridge National Laboratory in Tennessee, the U.S.-based Frontier supercomputer fell from second to third place. As before, Frontier achieved 1.353 Exaflop/s of performance. This system is based on HPE’s Cray EX235a system with AMD’s CPUs and Instinct MI250X accelerators.

Then, the U.S.-based Aurora supercomputer at Argonne National Laboratory holds the No. 4 spot at 1.012 Exaflop/s. Aurora is built by Intel. The system is based on the HPE Cray EX - Intel Exascale Compute Blade, which uses Intel’s Xeon CPU Max Series processors and Intel’s GPU Max Series accelerators communicating through Cray’s Slingshot-11 interconnect.

JUPITER Booster, operated by the Jülich Supercomputing Center under the EuroHPC Joint Undertaking, moves to No. 5 at exactly 1.000 Exaflop/s, remaining Europe’s only system above the exascale threshold on HPL.

Meanwhile, in the TOP500 rankings, U.S.-based HPE is the dominant system integrator, supplying six of the world’s most powerful systems. Supercomputers from Europe, the United States and elsewhere tend to incorporate merchant processors (AMD, Arm, Intel) and/or GPUs (AMD, Nvidia).

In contrast, supercomputers from China tend to incorporate proprietary processors. These systems tend to incorporate as many processors as possible, thereby driving up the performance levels.

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Supercomputers vs quantum computers

Supercomputers are not new. These systems have been in the market for decades. Generally, supercomputers incorporate traditional processors, memory and other components. In simple terms, these systems process and store data using the traditional binary language (1 or 0) approach.

In contrast, quantum computers use an internal device called a qubit to encode and process data. A qubit can represent a “0” or “1” or a superposition of both states simultaneously. Thus, in theory, quantum computers can outperform a classical computer. But quantum computers are still in the development stages.

Today’s quantum computer companies are based in China, the European Union (EU), Japan, the U.S. and other nations. It’s imperative for each country to gain a leadership position in quantum computing. In fact, the governments in China, EU, India, Japan and the U.S. are separately funding various quantum computing programs.

In a major boost for the quantum computing industry in the United States, the U.S. Department of Commerce recently announced the signing of nine letters of intent to provide $2.013 billion in federal incentives under the CHIPS and Science Act.

Still, for the foreseeable future, traditional supercomputers will remain the mainstream computing systems for high-end computing tasks.

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Teledyne MEMS, a MEMS foundry vendor, is expanding its manufacturing operations in Canada with funding from the Government of Alberta.

The expansion will enhance Teledyne MEMS’ advanced manufacturing capabilities in Edmonton, the capital city of the Canadian province of Alberta. The investment is backed by a CA$620,000 (US$435,674) grant from the province’s Investment and Growth Fund.

The expansion includes new wafer processing systems, inspection and automation equipment alongside facility upgrades. This in turn will help meet rising global demand for micro electro-mechanical systems (MEMS) sensors and microfabricated semiconductor devices.

MEMS are tiny devices that integrate mechanical and electromechanical elements in the same unit. The MEMS business is a critical technology sector that often flies under the radar.

Teledyne MEMS is part of Teledyne Technologies, a U.S.-based supplier of digital imaging sensors, industrial cameras, electronic test and measurement equipment, aircraft information management systems, and defense electronics and satellite communication subsystems.

Teledyne MEMS is a MEMS foundry, offering design, prototyping and high-volume manufacturing for MEMS sensors, actuators, and other components. It operates over 41,000 square feet of clean room space, using both 150mm and 200mm wafers.

Teledyne MEMS serves customers across automotive, industrial, medical, consumer, and communications applications.

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More MEMS

Separately, Teledyne MEMS has been selected as the MEMS partner for two recipients of the latest FABrIC Challenge funding awards announced by CMC Microsystems through the Government of Canada’s FABrIC initiative.

FABrIC (Fabrication of Integrated Components for the Internet’s Edge) is a Strategic Response Fund initiative designed to strengthen Canada’s domestic semiconductor capabilities and accelerate commercialization in areas including MEMS, photonics, compound semiconductors and quantum technologies.

Noze and Sheba Microsystems were selected as recipients of FABrIC Challenge funding to advance MEMS-enabled technologies in healthcare and automotive imaging. Noze is developing a high-resolution, scalable silicon aroma sensor for non-invasive, breath-based health monitoring and early disease detection, while Sheba Microsystems is developing MEMS actuators that provide AI-based temperature compensation for enhanced ADAS automotive camera systems, improving image focus and performance across changing environmental conditions.

Teledyne MEMS will support both projects through advanced MEMS process development and manufacturing expertise.

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Quantum Computing Inc. (QCi), a quantum optics and photonics company, has acquired NHanced Semiconductors, a U.S-based advanced packaging vendor.

Under the terms, QCi has acquired NHanced for $73.1 million in cash and stock, subject to customary adjustments, and up to an additional $72.0 million if certain performance targets are achieved.

Based in Batavia, IL, NHanced will operate as a wholly owned subsidiary of QCi, remaining committed to supporting its current customers and partners, including those within the quantum ecosystem, and will continue to provide the products, services and technical expertise its customers rely on while pursuing new opportunities for growth and innovation.

Based in Hoboken, N.J., QCi is a quantum optics and integrated photonics company focused on delivering quantum machines and photonic solutions. It offers a portfolio spanning photonics components, subsystems and full-stack systems. The company also provides foundry services for thin-film lithium niobate (TFLN) photonic chips.

The acquisition of NHanced expands QCi’s portfolio. The company is adding semiconductor and nanophotonics fabrication capabilities, advanced packaging expertise and specialized engineering talent.

NHanced is a U.S-based advanced packaging foundry specializing in integration, hybrid bonding, chiplet architectures, silicon interposers and photonics device integration. Its expertise in advanced semiconductor packaging and manufacturing complements QCi’s photonic and quantum portfolio.

“By combining our expertise with QCi's vision for photonic and quantum technologies, we believe we can accelerate the commercialization and manufacturing of next-generation solutions and create greater value for customers and partners,” said Bob Patti, CEO of NHanced.

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Nearfield Instruments, a supplier of metrology equipment, has closed a $380 million Series-D funding round.

This latest round of funding was led by a new investor Fidelity Management & Research, along with Temasek, Walden Catalyst Ventures, Innovation Industries, M&G Investments and Invest-NL.

Qatar Investment Authority (QIA) participated in this round as a new investor. Other existing investors, TNO Ventures and ING, also contributed to the round.

Nearfield Instruments was founded in 2016 as a spin-off of TNO, an R&D organization. Based in Rotterdam, the Netherlands, Nearfield Instruments specializes in advanced metrology and inspection tools for the semiconductor industry.

The company is shipping a next-generation scanning probe microscopy system for 3D nanometer-scale metrology. Nearfield’s system, called QUADRA, enables non-destructive atomic force microscopy (AFM) with full 3D imaging capabilities, including full side-wall measurement.

This allows semiconductor manufacturers to measure complex structures, such as high-aspect-ratio trenches, vias, and multi-layered stacks, in advanced chips and packages.

The new funding round will accelerate Nearfield’s roadmap, establish worldwide centers of excellence, expand production capacity, and strengthen its global customer support organization.

The funding values the company at $1.6 billion.

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AMD this week acquired MEXT, a startup that is developing AI-driven memory optimization technology.

The deal will bring new capabilities to AMD, a processor supplier based in Santa Clara, Calif. Founded in 2023, MEXT recently released its first product, dubbed Predictive Memory. MEXT’s technology is a software-only solution that makes flash appear as DRAM to the operating system.

It addresses a major problem in today’s systems--DRAM. DRAM, which is used as main memory in systems, is fast but it’s also a volatile memory type. That means the data is lost in the device when the system is shut down. Then, when a system is running, a DRAM is refreshed every few milliseconds to retain data. This increases power consumption and latency in systems.

“For modern workloads, performance is increasingly constrained not by CPU speeds, but by DRAM capacity,” according to MEXT, a startup based in Santa Clara, Calif. “On top of that, DRAM is one of the most expensive computing resources. For such a costly resource, the expectation would be that it would be well-utilized. In many environments, however, that is not the case.”

Studies from cloud providers have shown that utilization often drops to 50% or lower—over half of the memory can be considered cold, according to the company. This means that organizations are deploying much larger DRAM footprints than they truly need—resulting in potentially millions of dollars in wasted spend, according to MEXT.

MEXT’s Predictive Memory product line attacks the DRAM problem by transparently bringing flash into the memory domain. “Much like how large language models predict the next logical word in a natural language pattern, MEXT’s AI engine predicts the next logical memory page in a workload’s behavioral pattern,” according to the company.

According to MEXT, the process works in three steps: MEXT identifies memory pages that are not actively in use (cold) and offloads them to flash, which costs 50x less than DRAM. MEXT’s patent-pending AI engine predicts which offloaded memory pages will be needed soon. The engine proactively pushes those pages back to DRAM before they are required, so the application experiences little to no performance impact.

“Modern data center infrastructure is evolving rapidly, and customers are increasingly facing a common challenge: access to memory,” said Dan McNamara, senior vice president and general manager of Compute and Enterprise AI at AMD, in a blog. “As AI models, data analytics, virtualization and high-performance computing workloads grow in size and complexity, memory has become a critical constraint across cloud and enterprise environments. For customers, addressing these bottlenecks is essential to improving performance per dollar, increasing efficiency and accelerating deployments at scale.”

MEXT’s approach, according to AMD, has the potential to reduce infrastructure costs, improve resource utilization, and help customers more effectively scale general-purpose and AI workloads.

The acquisition expands the AMD’s portfolio and helps customers with memory optimization technology designed to improve performance, reduce total cost of ownership and accelerate time to deployment.

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Intel has reorganized its foundry unit and appointed a new executive to lead its efforts in the advanced packaging business.

Seok-Hee Lee, formerly president and chief executive of SK On, has been appointed as executive vice president of Intel Foundry, reporting directly to CEO Lip-Bu Tan. In this role, Lee will lead all advanced packaging, system integration, back-end technology development and back-end manufacturing at Intel Foundry.

Lee appears to have assumed the packaging leadership duties from Naga Chandrasekaran, executive vice president of Intel Foundry.

Previously, Chandrasekaran was in charge of the front-end manufacturing operations, packaging and other functions at Intel Foundry. With the changes, Chandrasekaran will continue to lead front-end technology development and manufacturing at Intel Foundry. Chandrasekaran will also continue to oversee design enablement and end-to-end customer-facing and business enablement functions that support Intel Foundry’s growth. He will continue to report to Tan.

All told, Intel Foundry appears to have split its operation into two groups. Chandrasekaran is in charge of the front-end fab duties, while Lee is leading the packaging business. Lee joins Intel from SK On, a global battery and trading company. Lee also served as president and CEO of SK hynix. He has also held engineering leadership roles at Intel and in academia.

The changes were made for several reasons. Intel is establishing advanced packaging as a focused business with dedicated leadership. This reflects the growing importance and complexity of packaging as a key enabler.

“Advanced packaging and system integration are becoming defining capabilities for next-generation computing systems,” Tan said. “Seok-Hee brings deep expertise in leading complex, high-scale technology and manufacturing organizations, along with a strong track record of operational execution. Seok-Hee’s insights will help Intel further strengthen our system integration capabilities, allowing us to tightly couple leading-edge logic, memory, networking, and other components to build high-performance computing systems for Intel Foundry customers.”

As part of the announcement, Intel also shared that executive vice president Navid Shahriari will be retiring after a 37-year career at the company.

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SandboxAQ, a supplier of platforms for materials discovery applications, has received government funding to accelerate the development of its technology.

The U.S. Department of Commerce’s CHIPS Research & Development Office signed a definitive agreement with SandboxAQ for a $500 million award under the CHIPS and Science Act. In connection with the award, the U.S. government will receive a minority, non-controlling equity stake in SandboxAQ, a Palo Alto, Calif.-based startup.

SandboxAQ’s core team came from Alphabet, the parent holding company of Google. The startup emerged as an independent capital-backed company in 2022.

Meanwhile, the CHIPS award will accelerate the development and deployment of SandboxAQ’s Al-driven materials discovery platform.

“Traditional materials discovery is often too slow for the demands of AI hardware, computing, and power electronics, which continue to accelerate,” according to the company. “At SandboxAQ, we take a different approach from traditional materials discovery methods. We apply Large Quantitative Models, or LQMs, to semiconductor materials discovery.”

The result is a platform built to deliver reliable answers faster and at greater scale than traditional methods alone.

For the CHIPS program, SandboxAQ will address critical semiconductor materials bottlenecks and supply chain risks, including developing new molecules and chemistries for alternatives to PFAS “forever chemicals,” advanced catalysts, rare earth-free magnets, and novel battery chemistries for semiconductor facility backup power systems.

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At this week’s VLSI Symposium, Intel Foundry provided an update on its process roadmap, including the status of its new 18A-P technology.

Targeted for the foundry market, Intel’s 18A-P process has entered risk production. The 2nm-class process enables high-performance chips with lower power. It also features a new dual contact, low resistance transistor option.

Based in Santa Clara, Calif., Intel is a supplier of processors for PCs and servers. The company also has a foundry unit, which is called Intel Foundry.

Foundry vendors make chips for other companies in large facilities called fabs. TSMC, Samsung, SMIC, UMC, GlobalFoundries and others compete in the foundry business. So far, Intel has struggled to get a foothold in the competitive foundry business, but the company’s fortunes could change with its new 18A-P technology.

18A-P is a new derivative of Intel’s 18A technology. Introduced last year, Intel’s 18A process is a 2nm-class technology. It combines a gate-all-around (GAA) transistor architecture with a backside power delivery technology.

Earlier this year, Intel launched its Core Ultra Series 3 processor line, marking the debut of the company’s first chips built on its new 18A process technology. Intel’s processor is codenamed Panther Lake.

The 18A process is more or less optimized for Intel’s own processor lines. In contrast, 18A-P is optimized for the leading-edge foundry market.

“Intel 18A-P builds on the same GAA and backside power foundation while remaining design-rule compatible with Intel 18A. This enables customers to gain performance benefits without redesigning entire layouts or libraries,” said Lori Scott, senior director of marketing at Intel Foundry, in a blog.

Intel 18A-P delivers 9% higher performance at iso-power or 18% lower power at iso-performance compared to Intel 18A.

“Intel 18A‑P also introduces material innovations that deliver 20-40% improvement in thermal resistance of the overall stack when combined with enhanced electronic design automation (EDA) workflows, building on earlier improvements introduced with Intel 18A,” Scott said.

“Intel 18A-P also features Power Boost, the industry’s first implementation of a novel dual contact architecture. Enabled by PowerVia backside power delivery, low-resistance frontside and direct backside contacts show improved resistance for both NMOS and PMOS transistors compared to Intel 18A. Intel 18A-P enables enhanced performance at matched footprint for power-constrained applications including mobile, AI accelerators, and data centers,” Scott said.

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TSMC and Amkor Technology have formed a major and long-term partnership in the advanced packaging and test arena in the United States.

The 10-year agreement establishes a collaboration framework for TSMC to procure from Amkor advanced packaging and testing services. The partnership centers around Arizona, where each company is separately developing a major manufacturing base.

Today, TSMC, the world’s largest foundry vendor, manufactures a large percentage of its chips in Taiwan. Then, in the U.S., TSMC is currently manufacturing advanced chips in its first fab in Arizona. The company is also building three more fabs in Arizona. Plus, TSMC plans to build an advanced packaging facility in the same location.

Meanwhile, Amkor, a large U.S.-based OSAT, is building a large-scale advanced packaging and test campus in Peoria, Ariz. In Arizona, Amkor is expected to manufacture advanced packages in early 2028. OSATs provide third-party packaging and testing services for the semiconductor industry.

In Arizona, TSMC and Amkor are in close proximity to each other. Peoria is a major suburb of Phoenix. TSMC’s fab site is located in Phoenix.

Nonetheless, TSMC and Amkor this week announced a major 10-year agreement. “This includes a structured approach for TSMC to procure advanced packaging and test services from Amkor, along with coordinated capacity expansion and planning,” according to officials from Amkor, based in Tempe, Ariz.

By working together as partners to expand capacity, the companies aim to enable a more efficient, mutually beneficial operating model while strengthening their ability to support customers’ evolving requirements.

“This agreement marks an important next step in our partnership with TSMC as we accelerate advanced semiconductor manufacturing in the U.S. to provide our customers a full U.S. supply chain from advanced silicon manufacturing to tested packaged devices,” said Kevin Engel, chief executive of Amkor.

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Fueled by the ongoing boom in the AI market, TSMC extended its commanding lead in the worldwide foundry business.

TSMC’s market share in the overall foundry business reached 72.3% in the first quarter of 2026, up from 70.4% in the previous quarter, according to a new report from TrendForce, a market research firm.

Taiwan’s TSMC, the world’s largest foundry vendor, continues to lead the market by a wide margin. Several other foundry vendors lost share during the quarter.

In general, foundry vendors make chips for other companies in large manufacturing facilities called fabs. For example, TSMC manufactures chips for Amazon, AMD, Apple, Broadcom, Google, Intel, Nvidia, Qualcomm, Tesla and many others.

Meanwhile, in first quarter of 2026, Samsung was in second place in the foundry business with 6.5% share, followed in order by SMIC (5.1%), UMC (3.9%), GlobalFoundries (3.3%), HuaHong Group (2.5%), Tower (0.8%), Nexchip (0.8%), VIS (0.8%) and PSMC (0.8%), according to TrendForce (See rankings chart below).

Intel, which is attempting to make inroads in the foundry business, is not in the top ten rankings. Rapidus, a foundry startup based in Japan, is still developing its first technology.

Typically, the semiconductor industry experiences a seasonal slowdown in the first quarter. “Although smartphone seasonality remained a headwind, the impact was largely offset by early inventory replenishment across consumer electronics supply chains,” according to TrendForce. “As a result, the traditional seasonal slowdown was notably muted, with combined revenue of the world’s top 10 foundries rising 3.7% QoQ to US$47.95 billion, setting another quarterly record.”

Robust demand for foundry services is expected to continue in the second half of 2026. At the same time, foundry vendors are dropping hints about possible wafer price increases in the second half. “This development is likely to encourage customers to place orders early in anticipation of upcoming price rises,” according to the firm.

In the meantime, check out the latest edition of “The Foundryecosystem Report.” This report provides a snapshot of the latest announcements in the foundry and packaging markets. (The report is free for readers.)

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Who is doing what?

The market dynamics are different for each foundry vendor. Here are some highlights for the leading foundry vendors in the first quarter of 2026 and beyond:

TSMC

TSMC’s revenues increased 6.3% quarter-over-quarter to nearly $35.86 billion. During the quarter, the foundry giant benefited from sustained demand for AI chips, including AI accelerators, GPUs and processors.

At present, TSMC is ramping up its new 2nm process. Apple is one of the first customers for TSMC’s 2nm technology.

TSMC, however, is seeing huge demand for its older 3nm process. In fact, the company is struggling to keep up with the demand here, causing it to build more fab capacity for the technology.

Meanwhile, at a recent event, TSMC released its latest technology roadmap. The roadmap consists of several new process technologies, including A13. Slated for 2029, A13 represents the company’s most advanced process technology.

Since the 7nm node in 2019, TSMC has been making leading-edge chips using ASML’s 0.33 NA extreme ultraviolet (EUV) lithography systems. This is sometimes called low-NA EUV.

At the A13 node, TSMC will continue to use ASML’s 0.33 NA EUV tools. For A13, TSMC doesn’t plan to use ASML’s more advanced high-NA EUV lithography tools. In fact, TSMC has been critical of high-NA EUV, saying the technology is too expensive.

Behind the scenes, though, TSMC is working on high-NA EUV. In R&D, TSMC is working on the next node, dubbed A10. “We note that TSMC is expected to use high-NA in its A10 (~2030 production), while fully remaining on low-NA at A14,” said Krish Sankar, an analyst at TD Cowen, in a research note.

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Samsung Foundry

South Korea’s Samsung is the world’s second largest foundry vendor. During the first quarter, Samsung’s foundry revenue declined 5.8% quarter-over-quarter to slightly over $3.2 billion.

Samsung continues to lose money in the foundry business. According to various reports in the media, Samsung’s management indicated that the foundry business may become profitable in 2028.

In the foundry business, Samsung’s market share slipped to 6.5% in the first quarter. “Samsung Foundry (excluding System LSI) also received some pull-in orders from TV and PC/notebook supply chains,” according to TrendForce. “However, these gains were largely offset by smartphone seasonality.”

At present, Samsung is ramping up its new 2nm process. Qualcomm, Tesla and others plan to use Samsung’s 2nm process.

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SMIC

SMIC, China’s largest foundry vendor, received pull-in orders from TV brands and PC/notebook customers during the first quarter. “Furthermore, wafer price increases negotiated with some 8-inch customers in 2H25 began taking effect,” according to TrendForce.

SMIC is in the process of acquiring Semiconductor Manufacturing North China (Beijing) Corp., or SMNC. Based in China, SMNC is a foundry vendor that owns and operates two 300mm lines. The company produces chips using 28nm processes.

SMIC already owns a 51% stake in SMNC. SMIC plans to acquire the remaining 49% stake at 40.6 billion yuan (US$5.97 billion), according to the South China Morning Post.

UMC, GF, HuaHong

In the rankings, Taiwan’s UMC, U.S.-based GlobalFoundries and China’s HuaHong were in fourth, fifth and sixth place, respectively.

“UMC benefited from inventory-building activities across TV and PC/notebook supply chains, receiving additional orders from both 8-inch and 12-inch peripheral IC customers. However, a higher proportion of 8-inch wafer shipments reduced ASPs by approximately 5%, resulting in a 3.2% QoQ decline in revenue to $1.93 billion,” according to TrendForce.

“GlobalFoundries saw fewer benefits from consumer electronics inventory replenishment due to its customer mix and was also affected by seasonal weakness in smartphone-related peripheral IC demand,” according to the firm. “HuaHong Group’s subsidiary, HHGrace, recorded modest wafer shipment growth that was largely offset by ASP declines, resulting in revenue remaining broadly stable.”

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The foundry industry is an important part of the semiconductor business. IC packaging is also important.

Nearly every week, there are several new and major announcements in the semiconductor foundry and packaging markets.

To help the industry, Semiecosystem has released the latest edition of “The Foundryecosystem Report.” This report provides a snapshot of the latest announcements in the foundry and packaging markets. (The report is free for readers.) Here’s what this report covers:

1—China’s Huawei plans to develop 1.4nm chips using the Tau (τ) Scaling Law and LogicFolding. What does that all mean? TechInsights weighs in.

2—Does the math add up for Musk’s Terafab project?

3—The EU rolls out Chips Act 2.0.

4—GlobalFoundries announces several deals.

5—Applied Materials expands in Singapore.

6—JCET expands into 3D integration.

7—UCLA unveils a new semi hub.

8—Global chip sales grew in Q1 (memory vs non-memory).

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Huawei’s ambitious plans

At a recent event, He Tingbo, president of the Semiconductor Business Department at China’s Huawei, described a methodology to develop chips at the 1.4nm node and perhaps beyond.

This methodology centers around two key concepts--the Tau (τ) Scaling Law and LogicFolding. Both concepts are designed to circumvent traditional geometric or chip scaling. Using these methodologies, Huawei hopes to develop chips with a transistor density that is equivalent to the 1.4nm process node by 2031.

Huawei’s presentation, however, raised more questions than answers. What is the Tau (τ) Scaling Law? What is LogicFolding? And how can Huawei develop chips at the 1.4nm node by using these concepts?

Before answering these questions, let’s briefly look at the challenges facing Huawei and others in China in terms of advanced semiconductor technology. First, Huawei designs its own leading-edge chips. But the company is unable to use TSMC as a leading-edge foundry vendor, due to a series of complex export control regulations.

So, Huawei has no other choice but to have its chips made by SMIC, China’s largest foundry vendor. Yet, SMIC’s most advanced process in production is a 7nm finFET technology. In R&D, SMIC is developing a 5nm process.

All told, SMIC--and China as a whole--are stuck at the 7nm and/or 5nm node.

To develop chips beyond the 5nm node, SMIC would need more advanced semiconductor manufacturing equipment. Simply put, the company requires ASML’s extreme ultraviolet (EUV) lithography systems. The problem? China is unable to obtain ASML’s EUV lithography scanners, due to export control regulations.

So, how can China circumvent the traditional methods of making leading-edge chips? To answer that question, I reached out to Dan Hutcheson, vice chair at TechInsights, a market research firm. In an e-mail exchange, here’s what Hutcheson said:

Semiecosystem: What exactly is Tau Scaling?

Hutcheson: Tau Scaling is simply a shift from geometric scaling to temporal scaling (τ). It takes you back to the 60s and 70s, because Moore’s Law was about geometric scaling, which doubled transistors for roughly the same areal cost, hence cutting the cost of a transistor. In contrast, Dennard’s Scaling Laws were a combination of temporal and power scaling. He pointed out that shrinking transistors puts them closer together, so they operate faster and use less power. What He Tingbo was essentially saying is that there are alternatives to shrinking to making chips faster. At its core, there is little new here, or as I wrote in The Chip Insider, ‘Huawei has just learned Electrical Engineering and now wants to teach the world.’

Semiecosystem: What is LogicFolding? Does it resemble TSMC’s SoIC technology (i.e. 3D heterogeneous integration, chiplets and hybrid bonding)?

Hutcheson: As a substitute for Moore’s Law scaling, LogicFolding uses heterogeneous integration (HI) to move critical blocks of transistors closer to each other by stacking them on top of each other. Again, nothing new here conceptually, but really new in branding and execution. At an execution level, Western approaches to HI have mostly been to shrink what used to be board-level integration down into a single package of chiplets. SoC designs are still done on a 2D plane. LogicFolding’s significant difference is designing the SoC with its critical timing paths on a 3D plane. As I wrote in The Chip Insider, chip stacking is already used in HBM. It’s less common for logic because of thermal issues. So, He’s Tau Scaling and LogicFolding concepts are definitely feasible and may deliver a good enough solution, but not best in class with older node technology.

Semiecosystem: Does Huawei’s technology somehow change the game? In other words, will it allow the company to play catch-up in logic scaling? Or is it much ado about nothing?

Hutcheson: He Tingbo’s LogicFolding concept is a wake-up call to Western EDA players, who have been moving in this direction, but at a slower pace. I’ve been writing about the need for HI since 2015 and I’m not the only one. But the arrival of EUV and renewed pace in shrinking allowed the West to pullover into an innovation rest stop. Restricting access to EUV and leading-edge chips forced Huawei to stay on the innovation fast lane. They have yet to pass us, but they will if we don’t get back into the fast lane.

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Fuzzy logic

Meanwhile, Elon Musk recently announced plans to build a new and giant fab. As reported, the fab project, called the Terafab, is a joint effort between Tesla and SpaceX. Musk’s goal is to build a large semiconductor fab in Austin, Texas--at a cost of $20 billion to $25 billion. A fab is a large facility used to manufacture chips.

The proposed Terafab is expected to manufacture both logic and memory chips all in the same facility. Initially, the goal is to produce logic chips at the sub-2nm node. And if that isn’t enough, the same facility will also package and test these chips.

Intel will apparently become a manufacturing and packaging partner for the Terafab project. Intel’s 14A process technology will play a big role in the project.

On its website, Tesla has several job postings for the Terafab. Musk has apparently talked to equipment vendors about obtaining tools for the fab.

All of this sounds exciting, right? A new U.S. fab with plenty of high-paying jobs!

The problem? Musk’s ambitious fab plans still appear to be unrealistic. The math simply doesn’t add up, at least according to one analyst.

In a new research note, an analyst from TD Cowen crunched various numbers based on Musk’s Terafab projections. This was billed as a “thought experiment,” not a definitive forecast. Here’s what the raw numbers say:

“SpaceX’/TSLA’s goal is to build a semiconductor facility spanning logic, memory, and packaging, ultimately capable of producing up to 1 TW per year of AI compute (~50x this year’s industry deployment). That is obviously far beyond anything the industry is deploying today, which is why we think the right way to look at it is as a ceiling thought experiment, not a base-case forecast,” said Krish Sankar, an analyst at TD Cowen, in the research note.

“Based on our 1 GW framework, we estimate that 1 TW would be equivalent to roughly 6M NVL72s of Vera Rubin, requiring ~3.5M wspm of front-end wafer capacity for GPUs/CPUs and ~10M wspm of HBM. We estimate that meeting that goal would require ~$1.5T of WFE (wafer fab equipment),” Sankar said.

“More broadly, our work suggests that a scaled version of Terafab could require ~950 litho tools (~200 High-NA, ~150 low-NA, and ~600 DUV), assuming each High-NA replaces roughly three low-NA layers,” Sankar said.

None of these figures are realistic. Not even close. Even the near-term goals seem unrealistic. “Near term, it has been reported that SpaceX intends to invest $55B in Grimes County, Texas as part of the initial buildout. Based on our fab cost breakdown, we estimate that could translate into ~ $35B of construction spend and $20B of WFE over 2028–29. Assuming a 50/50 split across logic/DRAM, it could imply 50K wpm of logic capacity and ~100K wpm of DRAM,” Sankar said.

All told, Musk may end up building the Terafab. But it won’t be as majestic as previously thought. The Terafab may turn out to be something different than what Musk is talking about.

Botton line: Get a more realistic picture of the Terafab before you accept any equipment orders or get a high-paying job offer. The Terafab may prove to be a lucrative endeavor. Find out if it’s for real or not.

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EU Chips Act 2.0

The European Commission (EU) has released its proposals for the new European Chips Act 2.0. The proposals introduce new measures to further boost the semiconductor industry in the European Union (EU). It hopes to reduce strategic dependencies and support advanced chip production in the EU.

“The EU remains dependent on third countries in key areas such as advanced chip manufacturing or semiconductor design,” according to the EC. “Securing a stable chips supply is necessary to ensure that critical infrastructures and technologies remain secure, resilient and aligned with European values.”

The Chips Act 2.0 builds on the progress made by the original Chips Act and will both reinforce current European strengths and build capacity in cutting-edge semiconductor technologies.

You can download the full regulation proposal, the annexes, the impact assessment and a summary of this impact assessment here .

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GF deals

GlobalFoundries (GF), a U.S.-based foundry vendor, has made several announcements in recent times, including:

*GF has announced a strategic partnership with the U.S. Department of Energy’s Genesis Mission, the department’s initiative to accelerate scientific discovery through artificial intelligence and advanced computing.

*Sivers Semiconductors recently announced a strategic collaboration with GF to develop advanced silicon photonics solutions for the high-growth AI infrastructure market. Sivers Semiconductors’ laser arrays will be integrated into reference designs built on GF’s silicon photonics platform. The collaboration supports a range of optical connectivity architectures, including co-packaged optics (CPO), linear pluggable optics (LPO), and other emerging data center interconnect solutions. Sivers’ laser arrays will also be available in GF’s Silicon Photonics Co-packaged Advanced Light Engine (SCALE) platform for next-generation optical sub-assemblies and light engine architectures.

*GF has completed its previously-announced acquisition of Synopsys’ ARC Processor IP Solutions business. GF’s recent acquisition of MIPS, combined with ARC, brings together RISC-V processor IP, software tools, custom design and advanced manufacturing into a single offering.

*CEA‑Leti reaffirmed its collaboration with GF in the FAMES Pilot Line. GF continues to work on FD-SOI technology in the pilot line. The FAMES Pilot Line is designed to accelerate early‑stage research and development in advanced semiconductor technologies. CEA-Leti is the coordinator of the pilot line. Separately, CEA-Leti recently announced a major milestone in the evolution of 3D integration for high-performance computing (HPC), advanced smart-vision systems and artificial intelligence (AI), demonstrating a functional test vehicle utilizing die-to-wafer (D2W) hybrid bonding with pitches down to 1μm.

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Applied expands in Singapore

Applied Materials has expanded its manufacturing and R&D operations in Singapore.

Applied’s new US$500 million (S$600 million) Tampines Campus more than doubles the company’s advanced cleanroom capacity in Singapore. The new facility is already operating at volume production, according to Applied, a Santa Clara, Calif.-based supplier of fab equipment.

The facility expands the company’s global fab equipment manufacturing footprint, which also includes facilities in the United States, Europe, Israel and Taiwan.

Singapore 2030 plan

Over the past several years, Applied has nearly doubled its global manufacturing capacity.

Singapore is a major manufacturing center for Applied. In 2022, the company announced its “Singapore 2030” initiative—a multi-faceted plan to expand its operations in Singapore over the next eight years. The plan is targeted at strengthening the company’s global manufacturing and R&D capabilities, broadening its ecosystem partnerships in Singapore and promoting local workforce development.

Today, the Singapore campus features a large manufacturing cleanroom and production capacity along with R&D facilities. With the expansion, Applied anticipates adding approximately 1,000 new local jobs over the next few years.

Applied is also building a new R&D center in the United States. In recent times, Applied has announced several R&D partnerships for its R&D facility, dubbed the EPIC Center. Broadcom and SCREEN Semiconductor Solutions are the latest partners in the EPIC Center.

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JCET expands

JCET, China’s largest OSAT, has opened its new facility for high-density 3D system integration at its Jiangyin manufacturing base.

The new facility represents a big step in JCET’s ongoing expansion of advanced packaging capacity. The facility includes 7,000 square meters of cleanroom space and is expected to achieve production line readiness by the end of this month. It will provide advanced packaging technologies and services for applications such as power modules for AI data centers.

In a separate move, JCET launched its next-generation high-density 3D power module packaging and test solutions designed for AI data center applications. Built on JCET’s XDPKG-3DSiP (3D system-in-package) technology, the new solution integrates high-density multilayer interconnects with a three-dimensional module architecture to optimize power devices, passive components, interconnect structures and thermal paths within a compact package footprint.

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AI semi hub

Broadcom, Applied Materials, GlobalFoundries, Meta and Synopsys are partnering with the UCLA Samueli School of Engineering to establish a $125 million Semiconductor Hub aimed at accelerating research and workforce development in AI–powered chip technologies. The Semiconductor Hub will be based at UCLA. The initial five-year commitment will establish a long-term collaboration across the semiconductor ecosystem, spanning chip design, software, manufacturing, equipment and advanced materials.

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Semi growth in Q1

In total, semiconductor revenues grew 27% in 1Q26 from 4Q25 to reach $319 billion, according to Omdia, a research firm.

Memory revenue drove the increase, rising over 80% sequentially in 1Q26 from 4Q25, according to the research firm. “Removing memory IC revenue shows that the 1Q26 semiconductor market grew, but much more modestly. Non-memory semiconductor revenue grew just over 2% QoQ in 1Q26,” according to Omdia.

“Historically, revenue for both the overall semiconductor market and the non-memory portion declines in Q1 by approximately 4%. Some components performed at typical seasonal rates; Microcontrollers (MCUs), discretes, and optical markets saw slight to mid-single digit QoQ declines for the first quarter of the year. However, other components, especially those in the AI and data center ecosystem, outperformed the typical decline in revenue in the first quarter. This gave the non-memory side of the semiconductor market modest growth,” according to the firm.

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For decades, lithography has been an important part of the semiconductor industry. Lithography is a technology that is used to process and develop today’s chips. It is required to make the world’s most advanced chips.

Lithography is a complex business with a multitude of facets. To help the industry, Semiecosystem has compiled the latest and more significant company and technology announcements in lithography and related topics. Here’s the latest:

1—Is JSR up for sale?

2—More JSR

3—FEL Funding

4—Mask Trends

5—Mid-year forecasts—chips, memory, EUV

I have written about each of these topics below.

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Is JSR up for sale?

Japan Investment Corp. (JIC), the parent company of Japan’s JSR, is considering selling the supplier of photoresists and other products, according to a report from Reuters. Fujifilm and Mitsubishi Chemical are possible suitors for JSR, according to the report.

JIC declined to comment. “As your questions relates to a specific matter concerning JSR, JIC does not comment on individual cases, including the status of any review or related facts,” according to officials from JIC.

Based in Tokyo, JSR is a major supplier of electronic materials, including photoresists, chemical mechanical polishing (CMP) slurries, deposition products and others. The company also sells materials for displays, life sciences, optical products and plastics.

It’s been a topsy turvy period for JSR. In 2023, JIC, a fund backed by the government, acquired JSR for 903.9 billion yen (US$6.3 billion). Following those events, JSR was delisted and taken private.

In 2024, JSR posted a loss of 217.7 billion yen on sales of 388.8 billion yen. The deficit was mainly due to losses in its life sciences unit.

Then, in 2025, JSR rebounded and reported a net profit of 60.7 billion yen. In 2025, sales were 440.7 billion yen, up 13.3% over 2024. The growth was driven by demand for electronic materials and improved profitability in the life sciences group.

Nonetheless, a potential sale of JSR would have major implications in the semiconductor supply chain. In 2021, JSR acquired Inpria, a supplier of metal oxide photoresists for extreme ultraviolet (EUV) lithography. Then, in 2024, JSR acquired Yamanaka Hutech, a supplier of high-purity chemicals used in the semiconductor industry.

Last year, JSR formed a partnership with Lam Research. The companies will collaborate to integrate JSR/Inpria’s patterning resists and films with Lam’s etch and dry resist deposition technologies.

For years, the industry has touted metal oxide resists for EUV lithography. Yet, metal oxide resists have struggled to get a major foothold in the EUV market. For EUV, chipmakers tend to use traditional chemically amplified resists (CAR).

There is an opening for metal oxide resists, however. For the emerging high-numerical aperture (high-NA) lithography market, chipmakers (i.e. Intel, Samsung, SK hynix, TSMC) are evaluating several resist types, including CAR and metal oxide.

Time will tell if metal oxide resists will ever live up to its promises. Time will also tell if JIC will unload JSR.

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More JSR

U.S.-based Entegris and JSR recently entered into a non-exclusive cross-licensing agreement.

Under the agreement, Entegris and JSR’s Inpria unit will cross-license metal oxide resist patents, terminate current inter partes review challenges (IPR2025-00267), and explore collaborative opportunities on future photoresist materials.

The work is intended to span resist formulation, precursor synthesis and development, and possibly ultra-clean MOR-specific filtration along with associated delivery systems needed to ensure these new materials perform for EUV lithography applications.

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FEL funding

xLight, a U.S.-based startup that is developing a next-generation light source technology for EUV lithography, has officially received funding from the U.S. government.

This week, the U.S. Department of Commerce and the National Institute of Standards and Technology (NIST) announced the signing of a final award of $150 million in federal incentives to xLight under the CHIPS and Science Act.

The deal was expected. These incentives are for the construction and demonstration of a free-electron laser (FEL) prototype, an alternative light source designed to redefine the limits of EUV lithography. This award will support prototype construction at the Albany Nanotech Complex in New York.

Still in R&D, xLight’s technology is designed to generate EUV light in an FEL-driven particle accelerator. xLight’s EUV FEL light source produces 4x more power than today’s systems. Basically, an FEL is a high-power light source, which uses electrons to produce light at different wavelengths.

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Mask trends

Mike Hadsell, executive officer and COO of Tekscend, talks about IPOs, EUV and ArF mask equipment investments, AI and curvilinear trends, as well as offers career advice in a wide-ranging interview with Aki Fujimura, CEO of D2S.

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Mid-year forecasts—chips, memory, EUV

Believe it or not, we are heading towards the second half of 2026. So, it’s time to look at the mid-year growth forecasts for semiconductors and wafer fab equipment (WFE). It’s also time to look at the future capacity and shipment forecasts for ASML’s EUV lithography tools.

Here are the latest forecasts:

Semiconductors

Thanks to AI, the semiconductor industry is experiencing an unprecedent boom cycle.

In 2025, global semiconductor sales reached $795.6 billion, representing an increase of 26.2% over 2024, according to the World Semiconductor Trade Statistics (WSTS) organization.

Now, in its new forecast, the WSTS has raised its outlook for the semiconductor industry in both 2026 and 2027. The global semiconductor market is now projected to grow by a whopping 90% in 2026, reaching $1.51 trillion, according to the WSTS.

In its previous forecast, the WSTS predicted that the global semiconductor market would grow by more than 25% in 2026, reaching $975 billion.

The new 2026 forecast reflects the ongoing boom cycle in the AI market. The AI-related chip markets, such as accelerators, GPUs, processors and memory, are all seeing huge growth.

In 2026, the sharp upward acceleration is expected to be driven by the memory segment, which is forecast to surge by around 250% year-over-year, reaching more than $800 billion, according to the WSTS.

“Logic is expected to remain another major contributor, growing 37% in 2026,” according to the WSTS. “Other product categories are forecast to expand at more moderate rates, reflecting a broader industry growth: Microprocessors-20%, Analog-10%, Discrete Semiconductors-8%, Sensors and Optoelectronics with 3%.”

For 2027, WSTS forecasts the global semiconductor market to grow a further 27%, reaching approximately $1.9 trillion.

Memory

Suppliers of DRAMs, high bandwidth memory (HBM) and NAND flash memory are seeing enormous demand in the market. In fact, there are shortages of these products in the market, causing a spike in prices.

“The shift in AI development from large-scale model training toward inference-centric Agentic AI applications is driving a structural expansion in memory demand,” according to TrendForce. “With the resulting supply deficit unlikely to be resolved in the short term, prices are set to rise further.”

TrendForce, a research firm, has raised its global memory market forecasts, increasing its 2026 estimate from $551.6 billion in the previous report to $889.3 billion. Meanwhile, the 2027 forecast has been revised upward from $842.7 billion to more than $1.28 trillion, representing annual growth of approximately 44% (See chart below for DRAM and NAND forecasts).

Fab equipment

Fueled by AI and other markets, suppliers of semiconductor equipment have also seen robust demand.

In total, the wafer fab equipment (WFE) market reached $109.7 billion in 2025, up 10% over 2024, according to TD Cowen. Then, not long ago, TD Cowen projected that the WFE market would reach $136.6 billion in 2026, up 24% over 2025.

What’s next? “We think the buy-side view is that WFE grows from approximately $140 billion-plus this year to $180-200 billion in 2027 and potentially $200-230 billion in 2028,” said Krish Sankar, an analyst at TD Cowen, in a research note. “Management teams have not explicitly blessed these numbers, but (in general) did not push back on next year. There is a clear level of optimism, particularly from LRCX and AMAT regarding the WFE opportunity over the next few years.”

Nonetheless, here are some other data points for 2026:

“Front-end semicaps are raising pricing driven by component cost increases and value pricing. What seems different this time, is that the customers are not pushing back, given the strong demand for equipment,” Sankar said.

“We do not expect TSMC to raise WFE-related capex this year due to clean room restrictions at Fab 18 (P8) for N3 and tool availability,” Sankar said.

As reported, TSMC is seeing strong demand for its foundry services. In fact, the Taiwanese foundry giant is struggling to keep up with demand at the 3nm node.

EUV tools

Back in April, ASML posted robust results for the first quarter of 2026. At the time, the Dutch-based lithography giant raised its revenue growth outlook for 2026.

“The bullish view for ASML was not about this print specifically, but rather a multi-year increase in EUV-to-WFE intensity in both DRAM and leading-edge logic after two years of decline and we think that thesis remains intact,” Sankar said in a report.

Given that EUV intensity is back on track, there is a pressing question here: Does ASML have enough manufacturing capacity in place to meet demand for its EUV tools?

In 2026, ASML will have the capacity in place to build and ship 63 EUV tools, including 58 low-NA (0.33) systems and 5 high-NA products, according to TD Cowen. Then, to meet demand in 2027, ASML will have the capacity in place to build 81 EUV tools next year, including 75 low-NA systems and 6 high-NA systems, according to TD Cowen.

Let’s say the AI market remains robust. And let’s say WFE hits $220 billion in 2028. How many EUV tools are required to meet demand in 2028?

“Management highlighted +80 units next year, but to get to +$220B in 2028, we estimate it requires +90 EUV unit capacity,” Sankar said in a new report.

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Rapidus, a foundry startup based in Japan, has completed an additional funding round of 150 billion yen (US$943 million).

The funding came from the Information-Technology Promotion Agency (IPA), an independent administrative agency under the jurisdiction of Japan’s Ministry of Economy, Trade and Industry (METI).

Earlier this year, Rapidus received a 100 billion yen (US$623.7 million) investment from the IPA, in addition to private-sector funding, totaling 167.6 billion yen (US$1.05 billion) from 32 companies. This includes Canon, Development Bank of Japan, Fujitsu, NTT, SoftBank and Sony.

As a result of this latest capital increase by the IPA, Rapidus’ funding now totals 424.95 billion yen (US$2.65 billion).

Rapidus hopes to become a viable contender in the foundry business. The company is currently developing its first technology--a leading-edge 2nm gate-all-around (GAA) process (See Figure 1). The company’s 2nm process is expected to move into production in 2027. Its fab is based in Chitose, a Japanese city located in Ishikari Subprefecture, Hokkaido.

In addition, the company is also developing advanced packaging and chiplet technologies for foundry customers.

Figure 1. Rapidus’ 2nm process will use a gate-all-around (GAA) transistor structure, which will deliver high-performance and low-power chips. Source: Company

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More recent news

Meanwhile, Japan’s semiconductor industry is heating up. Besides the news at Rapidus, there have been several recent and major announcements in Japan, including:

*TSMC is building its second fab in Japan. TSMC plans to manufacture chips based on its 3nm process. Volume production is slated for 2028.

*Sony and TSMC intend to establish a joint fab venture in Japan. The goal is to manufacture CMOS image sensors.

*SoftBank’s subsidiary, SAIMEMORY, recently signed a collaborative agreement with Intel. The companies plan to commercialize ZAM (Z-Angle Memory), a next-generation memory technology designed for high capacity, high bandwidth and low power consumption. In addition, SAIMEMORY recently completed its Series A funding round, with Fujitsu, Development Bank of Japan, RIKEN and SoftBank as investors.

*Mitsubishi, Rohm and Toshiba Electronic Devices & Storage are in discussions to merge their power device and semiconductor businesses.

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Several universities have separately announced new and major research projects in the power semiconductor field.

Pennsylvania State University (Penn State), Purdue University, Texas Tech, University of Texas at Dallas, and the University of Warwick are the latest universities to expand their respective R&D efforts in the power semiconductor field. Basically, power semiconductors are specialized devices, which can withstand higher voltages and currents with lower losses in a system.

At these universities, students can get firsthand experience in this field. At the same time, universities work with companies and industry partners to develop new breakthroughs in the arena. See below for a description of what each university is doing here.

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What are power semis?

But first, let’s briefly talk about power semiconductors. These devices are used in nearly every system, including appliances, cars, chargers, computers, smartphones, solar panels, trains, wind turbines and others.

Power semiconductor devices are used to control the flow of electricity in systems. Power semis can withstand higher voltages and currents with lower losses in systems. Until recently, power semiconductors built around traditional silicon materials dominated the market.

More recently, several companies have been selling two new and different types of power semiconductor devices in the market—gallium nitride field-effect transistors (GaN FET) and silicon carbide MOSFETs (SiC MOSFET). Both GaN- and SiC-based devices fall under a general category called wide bandgap (WBG) semiconductors. WBG devices can operate at higher voltages, temperatures and frequencies, as compared to traditional silicon-based products.

In R&D, the industry is working on ultra-wide bandgap (UWBG) devices. Aluminum nitride (AIN), gallium oxide and diamond fit into the UWBG category. Potentially, UWBG devices can outperform GaN, SiC and silicon. But there are several challenges to produce UWBG devices (See figure 1).

Figure 1. Properties of silicon (Si), SiC, GaN, and Ga2O3. Source: U.S. Department of Energy

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To be sure, the power semiconductor industry is a complicated but interesting field. Here are the latest efforts at various universities:

UTD

The University of Texas at Dallas (UTD) has partnered with Attolight to open a new demonstration laboratory supporting the WBG semiconductor industry.

Located at UTD, the lab will offer advanced material characterization services and collaborative research opportunities. The lab is equipped to provide R&D contract work for industry partners and academic institutions seeking to accelerate their development cycles and improve device yields.

The lab will also help connect advanced university research with the needs of the regional semiconductor industry. It will prepare students for careers in the U.S. semiconductor workforce.

The UTD demo lab will host Attolight’s Allalin CL-SEM platform. The platform integrates a high-resolution scanning electron microscope with a proprietary, high-efficiency light collection and analysis system. This allows researchers to detect structural defects and analyze spectral properties at the nanoscale without damaging the samples.

“Attolight’s technology is based on cathodoluminescence spectroscopy,” according to the Swiss-based company. “Cathodoluminescence (CL) is a well-known phenomenon that refers to the light emitted by any material under electron irradiation. CL becomes a very powerful defect inspection method when implemented in a modern electron microscope (EM) that is capable of fast, non-destructive defect inspection on a full wafer scale.”

The system can be used for GaN, SiC and other materials. Besides the CL-SEM platform, UTD’s lab has other equipment, as well. “The lab currently has a substantial portion of the characterization and device fabrication capabilities needed for GaN and SiC research, including lithography, etching, metallization, and device/material characterization,” said Matthew Wong, an assistant professor at UTD.

“While GaN remains our primary focus, we are also actively working on several other wide-bandgap and ultra-wide-bandgap semiconductor materials,” Wong said in an e-mail exchange.

This includes:

*Gallium oxide for power electronics, radiation-tolerant devices and photodetectors

*AlN and AlScN for RF electronics, ferroelectric devices and next-generation power electronics

*Diamond-related technologies, particularly concepts involving integrated photonics and quantum sensing applications

“In addition, we have ongoing interests in emerging materials and heterostructures for photonics, microLEDs, power electronics, radiation-hardened devices, and semiconductor manufacturing technologies,” he added.

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Penn State

Germany’s Aixtron, a provider of deposition equipment to the semiconductor industry, announced that its new Close Coupled Showerhead (CCS) R&D-system will serve as the centerpiece of a new advanced semiconductor research facility at Penn State’s Materials Research Institute (MRI).

Aixtron’s CCS is a metal-organic chemical vapor deposition (MOCVD) system, which is geared for R&D and small-scale production.

The new laboratory, located in the Millennium Science Complex at University Park, will expand Penn State’s capabilities in next‑generation semiconductor thin films and device research.

It is being established through $4.3 million in infrastructure funding and support provided through the university’s membership in the Midwest Microelectronics Consortium (MMEC) – part of the U.S. Department of Defense’s Microelectronics Commons initiative under the federal CHIPS Act.

At the core of the facility is Aixtron’s CCS deposition system. The CCS R&D system is an epitaxial growth platform capable of depositing thin semiconductor layers on substrates with diameters of up to 100mm. The installed system is configured to grow GaN and two‑dimensional (2D) materials.

“The facility will serve as a national user platform, offering hands‑on training for students and early‑career researchers while providing industry‑standard process know‑how,” said Joan Redwing, Penn State’s Distinguished Professor of Materials Science and Engineering and of Electrical Engineering and Director of the University’s 2D Crystal Consortium research facility. Penn State’s main campus (University Park) is located in the borough of State College, in central Pennsylvania.

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Purdue

Purdue University recently announced a strategic partnership with Taiwan’s GeChi Compound Semiconductor (GCCS).

Under a memorandum of understanding (MOU), Purdue and GCCS will conduct research and development in the SiC arena. GCCS specializes in advanced SiC crystal growth and ingots.

GCCS will serve as a provider of semiconductor materials and Purdue as a hub for the technology. Purdue is located in West Lafayette, Indiana.

Joint research will focus on isolating crystal defects and optimizing SiC material growth to accelerate the transition to high-yield 200mm and 300mm wafer platforms. This collaborative framework ensures these academic breakthroughs in thermal management and material characteristics translate into high-volume manufacturing.

The MOU is for five years and will strengthen collaborative research and development between both sides as well as create academic-industry workforce development initiatives.

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Texas Tech

Texas Tech University has recently received $4.5 million from the Texas Semiconductor Innovation Fund (TSIF).

The funding will be used for a new project, entitled: “Research and Development of Wide/Ultrawide Bandgap Semiconductor Materials, Devices and Applications.”

Over the next three years, researchers will seek to increase Texas Tech’s capabilities to develop UWBG semiconductors for high-power/high-frequency electronics and optoelectronics. This work hopes to improve the performance and reliability of UWBG materials and high-electron-mobility transistors for harsh environments.

“At the same time, we feel a strong sense of responsibility: to translate discoveries into reliable, manufacturable technologies; to build workforce pipelines by training students and technicians, and to partner with industry and government to ensure our work delivers real-world impact for Texas and the nation,” said Hieu Nguyen, a professor at Texas Tech, which is located in Lubbock.

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University of Warwick

The University of Warwick of the U.K. recently secured funding to boost the ability to test the reliability of advanced semiconductors used in electric vehicles, renewable energy and other critical technologies.

The funding will support the purchase of a new test system from ipTEST Ltd. Based in the U.K., ipTEST makes the MOSTRAK series of testers. They are designed to test discrete MOS, IGBT, SiC, GaN and bipolar devices.

The new test system will enable researchers to put next-generation GaN and SiC power semiconductor devices through extreme test conditions to see how they perform, and when they fail.

The new equipment will be housed within Warwick’s Driving the Electric Revolution – Innovation Centre (DER-IC). It will be available to academic and industry users.

“By enabling fast, repeatable, and industry aligned reliability testing, this equipment will allow us to build the UK’s first comprehensive SiC and GaN reliability database. It also provides a foundation for new commercial services that will support UK manufacturers, SMEs, and international device suppliers alike,” said Peter Gammon, a professor at the University of Warwick.

Gammon is also a member of REWIRE IKC. REWIRE is an Innovation and Knowledge Centre (IKC) funded by UKRI, dedicated to pioneering next-generation semiconductor technologies and power electronic devices.

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Invisix--a soft X-ray metrology startup founded by former members of ASML--has raised €20 million (US$23.26 million) in new funding.

The investors include Hitachi Ventures, Transition Ventures, imec.xpand, Doosan Investment and others. The funding will be used to grow the Invisix team, accelerate the development of its first shippable X-ray metrology system, and support customer demonstrations at its new cleanroom in Eindhoven, the Netherlands.

Based in Eindhoven, Invisix is developing a soft X-ray metrology system for advanced logic and memory applications. The company’s system makes use of soft X-ray scatterometry, which uses X-ray techniques to see inside the buried nanoscale structures in chips. Then, the system will reconstruct detailed 3D information about the structure at high throughputs.

In general, metrology is an important part of the semiconductor industry. By definition, metrology is the science of measurement. Basically, in the semiconductor industry, chipmakers (i.e. Intel, Samsung, TSMC, others) install various types of metrology equipment in a fab. Metrology equipment is used to measure the tiny structures and complex materials in chips. Metrology equipment, along with other systems, helps ensure that a chip line can be produced with good yields.

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X-ray metrology spinoff

Meanwhile, founded in 2025, Invisix plans to commercialize an X-ray metrology system, which was in the works at ASML. In fact, this X-ray metrology technology had been incubating inside ASML since 2015.

At a conference in 2023, ASML gave a paper on its soft X-ray metrology technology. Intel was the co-author of the paper. The paper gave various results in collaboration with Intel and Imec.

Nonetheless, ASML’s soft X-ray metrology unit last year was spun-out into a new company called Invisix. Invisix was co-founded by Christina Porter and Sietse van der Post. Both Porter and van der Post were involved with the X-ray metrology program while working at ASML.

Porter, a former project leader and pathfinding architect at ASML, is chief executive of Invisix. Meanwhile, van der Post, a former technical architect at ASML, is the chief technology officer at Invisix.

Invisix has licensed a substantial technology package from work on soft X-ray technology performed at ASML. With the technology, Invisix is developing a new system. “We are building a soft X-ray metrology system, using a multicolor, laser-like light source operating at wavelengths between 9nm-19nm,” according to officials from Invisix. “Some would call this EUV (extreme ultraviolet); it is right on the boundary between SXR (soft X-ray) and EUV.”

The system is targeted for both advanced logic (gate-all-around, CFET) and memory (6F2 and 4F2 DRAM) applications, according to officials at Invisix.

Invisix’ system implements a technology called High Harmonic Generation (HHG). HHG uses a short-pulsed drive laser to excite noble-gas atoms into a high-energy state. In this state, the atoms emit short-wavelength light, known as soft X-rays. Invisix’ system combines HHG with proprietary reconstruction algorithms and machine learning to reconstruct the detailed 3D internal structure of devices. It achieves this in a non-destructive way.

The company recently relocated its 300mm-wafer-capable soft X-ray testbench to a new cleanroom in Eindhoven, where customer demonstrations will continue in parallel with development of its first shippable product for deployment in fabs.

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Why soft X-ray metrology?

To be sure, there is an urgent need for new metrology systems in the market, and for good reason: At each new generation, advanced logic and memory chips are becoming more complex and expensive.

As chip complexity increases, the ability to measure the tiny structures and materials in these devices has become more challenging. In many cases, the measurements are conducted at the angstrom level. An angstrom is 0.1nm.

To measure and characterize chips, semiconductor manufactures (i.e. Intel, Samsung, TSMC, others) use metrology equipment. But there is no one metrology tool that can handle all requirements. So, chipmakers use various types of metrology systems in the fab and the lab.

Some metrology tools are electron-based systems. Others use sophisticated optical techniques, while some are based on X-ray. X-ray metrology isn’t new. This technology has been around for ages. In fact, there are several different types of X-ray metrology tools in the market.

Soft X-ray scatterometry is a relatively new and promising technology. “Semiconductor manufacturers can’t build what they can’t see. As chips become more 3D, the industry needs a new generation of metrology tools that can look inside these incredibly complex miniature skyscrapers without destroying them,” Invisix’ Porter said. “We are entering the market with technology that has been incubated inside ASML for more than a decade — a level of technical de-risking that is unusual for a seed-stage hardware company and gives our customers a faster path to deployment.”

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South Korea’s Samsung has extended its lead in the booming DRAM business in terms of market share, according to Counterpoint Research, a market research firm.

In the overall DRAM business, Samsung’s market share reached 38% in the first quarter of 2026, up from 36% from the previous quarter and 34% in the like period a year ago, according to Counterpoint Research.

South Korea’s SK hynix was in second place in the DRAM market with 29% share, followed in order by U.S.-based Micron (22%) and China’s CXMT (8%), according to the research firm (see chart below).

“(Samsung and SK hynix) were in a close contest last year for leadership in DRAM revenue before Samsung reclaimed the top spot in Q4 2025,” said Jeongku Choi, an analyst at Counterpoint Research, in a new report.

Nonetheless, fueled by the AI business, DRAM suppliers have seen unprecedented demand--and growth--in the marketplace. In total, global DRAM revenues reached a record high of $97 billion in the first quarter of 2026, up 80% from the previous quarter and up 260% from the like period a year ago, according to Counterpoint Research.

“High bandwidth memory (HBM) and growing LPDDR5 content in AI data center infrastructure played key roles in driving this growth,” Choi said.

The demand has also caused DRAM suppliers to raise their prices in recent times. “DRAM average prices are continuously on the rise,” according to Counterpoint’s Monthly Memory Price Tracker. “Prices are expected to rise further in Q2 2026 by 50% QoQ (including both HBM and commodity DRAM), signaling another blockbuster quarter.”

Samsung remains on top in terms of DRAM market share. Source: Counterpoint Research

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What’s new in the DRAM biz?

To be sure, the DRAM market is a dynamic business. Nearly every week, there are several new and major announcements in the DRAM business. Here are just some of the recent announcements:

Samsung

In recent times, Nvidia has introduced its latest chips for the AI market, including the Rubin GPU. Nvidia will initially ramp Rubin with Samsung’s new HBM4 memory. In addition, AMD will align on Samsung’s HBM4 memory for its next-generation GPUs and server processors.

Then, in a separate move, Samsung is now shipping the industry’s first 12-layer HBM4E samples to major customers. Samsung’s HBM4 is built on its most advanced 6th-generation 10nm-class DRAM process (1c) and a 4nm logic base die.

Samsung’s HBM4E delivers a pin speed of 14 gigabits-per-second (Gbps), with performance scalable up to 16Gbps. This represents more than a 20% increase over its HBM4, while delivering memory bandwidth of up to 3.6 terabytes-per-second (TB/s) per stack.

Samsung’s 12-layer HBM4E is offered in a 48-gigabyte (GB) capacity, representing more than a 30% increase over the previous generation, with plans to expand the lineup to include 32GB (8-layer) and 64GB (16-layer) configurations in accordance with customer requirements.

SK hynix

SK hynix has launched its iHBM solution. This technology embeds integrated cooling elements (ICEs) within its HBM products.

Integrated cooling elements are made of electrically non-conductive, thermally conductive silicon-based material, designed to dissipate heat from the HBM package by providing an additional thermal path.

This technology solves a major problem. Heat management has become a critical challenge as HBM technology advances with higher stacking and faster speeds, according to the company.

“Existing HBM products rely on an indirect cooling method that draws heat away through the core die,” according to SK hynix. “In contrast, the iHBM solution places ICEs directly in the D2D PHY area where heat concentration is the highest, creating an additional heat dissipation path. This latest heat management solution helps reduce thermal resistance by 30% and enables chips to operate stably even in high-temperature and high-pressure conditions.”

Micron Technology

Micron has begun manufacturing its 1α (1-alpha) DRAM products at its fab in Manassas, VA.

Micron’s 1-alpha DRAMs aren’t new. The company originally introduced 1-alpha DRAMs back in 2021.

Still, Micron’s 1α (1-alpha) DRAM products are well suited for long-lifecycle memory for critical applications, including DDR4 and LP4 DRAM products. These products serve the automotive, defense/aerospace, industrial, networking and medical device sectors.

The industry still needs DDR4 DRAMs, and for good reason. For some time, there has been a shortage of these older DRAMs in the market.

CXMT

CXMT recently announced plans to file for an initial public offering (IPO) in China. The company’s IPO application has passed a review by the Shanghai Stock Exchange. CXMT plans to raise 29.5 billion yuan ($4.35 billion), according to the Global Times.

“AI growth is also helping CXMT capture the growing domestic DRAM demand in China – from smartphones to servers. CXMT is also receiving a top-line boost from rising DRAM chip prices, which was the most notable development in Q1 2026. CXMT’s DRAM revenue surged more than 700% YoY, cementing its position as a solid No. 4 supplier with its market share more than doubling to 8%,” Counterpoint’s Choi said. “The company is also gearing to raise significant capital via upcoming IPO filing to ramp up its capacity for DRAM production and enter the AI data center HBM market with full force in the coming years.”

Nanya

As reported, Cisco, Kioxia, Sandisk and Solidigm have separately invested in Taiwan’s Nanya Technology, a supplier of DRAMs. In addition, Kioxia, Sandisk and Solidigm have separately entered into DRAM supply agreements with Nanya. These companies hope to obtain a source of DRAMs to support their respective solid-state drives (SSDs).

Nanya is also building a new fab in Taiwan. The new fab is progressing on schedule, with equipment installation planned for the first quarter of 2027.

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The European Union (EU) has launched two new semiconductor R&D projects with several other initiatives in the works.

Germany’s Infineon is leading one R&D project, which is designed to develop new advanced packaging techniques for next-generation power semiconductor devices. Power semiconductors are specialized chips, which help control and convert electric power in systems.

Then, in a separate R&D project, CEA-Leti, Fraunhofer and Imec will lead the development of next-generation electronic components and systems, and accelerate their industrial adoption across Europe.

Here is a description of these two projects, as well as a smattering of other R&D initiatives taking place in Europe:

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Moore4Power

Europe has launched the Moore4Power project, an initiative that will develop new advanced packaging techniques, namely heterogeneous integration, for next-generation power semiconductor devices. Generally, chips are manufactured and then assembled into a package. Incorporating different and complex dies in an advanced package is sometimes called heterogeneous integration.

Led by Infineon, Moore4Power, or More than Moore for Disruptive Innovations in Power Electronics, is a project that consists of 62 European partners from 15 countries (Click here to see the participating members).

With a total project volume of €91 million (US$105.56 million), Moore4Power will run for three years. The project is co‑funded by grants from the participating countries and the Horizon Europe – Chips Joint Undertaking (Innovation Action) program.

At the core of Moore4Power is heterogeneous integration. The goal is to combine different semiconductor chip technologies, such as silicon, silicon carbide (SiC) and gallium nitride (GaN)--along with sensing, control and communication functions--to form integrated systems in a package.

Each technology is used where it performs best, enabling higher efficiency, improved reliability and more compact designs. This modular approach will pave the way for next-generation power chips in a range of applications.

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RESOLVE

Meanwhile, in a separate effort, eighteen research and technology organizations have committed to RESOLVE, a new European project designed to develop the next generations of electronic components and systems.

RESOLVE, or Reinforcing European SOvereignty and Leadership in Value added Electronics products, is led by CEA-Leti, Fraunhofer and Imec (Click here to see the participating members).

This project aims to position Europe as the global leader in future AI solutions, to improve by a factor of 1,000 the energy efficiency of electronic systems by 2032, and to strengthen European semiconductor production capacity.

RESOLVE is structured around two pillars:

*R&D and technology maturation—The goal is to develop 15 key technologies across the semiconductor and electronic systems value chain.

*From laboratory to industry/From industry to market—The goal is to ensure a rapid and effective transfer to the European industry. It also includes early involvement of industrial partners and alignment with product roadmaps and the co-development of prototypes.

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Other R&D projects in Europe

Here are just a few of the other projects in Europe:

*The European Commission (EC) has approved €288 million (US$335.23 million) in German State aid to fund two new facilities in the semiconductor supply chain. The funding will support Zeiss’ HNA@SCALE project, which will introduce and industrialize high-NA extreme ultraviolet (EUV) lithography columns. The funding will also support Zadient Materials’ investment project for the construction of a factory for ultra-pure silicon carbide (SiC) to be used as a semiconductor source material.

*The EU recently launched the SUPREME consortium. The goal is to develop a 200 qubit 3D integrated module, demonstrating progress towards large-scale superconducting quantum computers. VTT Technical Research Center of Finland is the coordinator of the project.

*The United Kingdom has launched the EXPRESS program, a five-year, £10.4 million (US$14 million) EPSRC-funded project led by the University of Warwick and University of Southampton. The program will explore new electrochemical approaches, combined with novel precursor chemistry, to grow transition metal dichalcogenides (TMDCs) - advanced layered semiconductors with potential applications in ultra-low-power electronics, neuromorphic computing, photonic circuits, and quantum technologies. TMDCs enable so-called 2D semiconductors, which are in R&D.

*Fraunhofer Institute for Photonic Microsystems IPMS has demonstrated the feasibility of quasi-monolithic integration (QMI). QMI refers to a technology in which different functional chiplets (CMOS, MEMS, non-silicon) are integrated into an almost monolithic system. The idea is to embed small chiplets into specially structured silicon pockets in a wafer. In the QMI flow, you start with a 200mm wafer. A multitude of tiny rectangular squares are formed and etched in the wafer. These tiny squares are known as pockets. Pre-fabricated and tiny chiplets are placed in these pockets and then bonded. The top is planarized and redistributed layers are formed on top.

*CEA-Leti and NcodiN, a French startup pioneering nanolaser-enabled photonic interconnects, recently announced a strategic collaboration to industrialize NcodiN’s optical interposer technology on a 300mm integrated photonics process. NcodiN is building NConnect, an integrated optical interconnect platform powered by the world’s smallest laser on silicon—500 times smaller than today’s devices. The company’s nanolaser-enabled photonic interposers pave the way to ultra-dense integration (>5,000 nanolasers/mm²) and record-low energy operation (~0.1 pJ/bit).

*U.S.-based Lam Research has established a Panel-Level Packaging Center of Excellence (CoE) in Salzburg, Austria. The Salzburg facility is Lam’s first panel-focused wet processing R&D site. The Salzburg site builds on the legacy of Semsysco, founded in Salzburg in 2012 and acquired by Lam Research in 2022. That acquisition added panel-level wet processing expertise and an additional European R&D base to Lam’s global laboratory network.

*Malta Government Venture Capital (MGVC) has approved an investment under its co-investment framework to support the growth of Quinas Technology. Quinas Technology is the commercial spin‑out of more than a decade of research originating at Lancaster University in the United Kingdom. The company is developing ULTRARAM, a novel ultra-low power non‑volatile memory technology that combines the speed and endurance of DRAM with the persistence of flash memory, addressing critical bottlenecks in AI and edge‑compute systems.

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Taiwan’s Advanced Semiconductor Engineering (ASE), the world’s largest OSAT, has launched an automated 310mm x 310mm panel-level packaging production line.

ASE’s automated panel-level packaging line supports the 310mm x 310mm format. The line is compatible with the company’s advanced packaging platforms, including its FOCoS and FOCoS-Bridge lines, delivering line/space capabilities of 2/2µm and 8/8µm, respectively.

ASE’s FOCoS line is a fan-out package, which is flip-chip mounted on a high pin count ball grid array (BGA) substrate. The FOCoS-Bridge line utilizes tiny silicon pieces with routing layers as in-package interconnect between chiplets.

The new panel line is expected to enter production in the first half of 2027, according to ASE. ASE and other OSATs provide third-party packaging and testing services for the semiconductor industry.

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PLP gains steam

ASE is seeing strong demand for its advanced packaging and testing services in the market. The demand is being driven by AI and other technologies. To meet demand, ASE is building or acquiring new facilities. For example, the company is building a new IC test facility in Kaohsiung, a city in southern Taiwan.

ASE and others are also ramping up or developing panel-level packaging (PLP) lines. PLP is a different way to manufacture advanced packages. Typically, in some advanced package types, multiple chips are processed and packaged on round 200mm or 300mm wafers.

In PLP, however, multiple chips are processed on a large rectangular substrate or a panel. PLP allows for more chips to be processed at the same time, thereby increasing the throughput. PLP also reduces manufacturing costs.

“This shift to panel-level packaging addresses critical industry challenges, including rising interposer sizes and declining wafer-level efficiency,” according to ASE. “The larger panel format supports higher throughput and reduced cycle time, while enabling integration of increasingly complex multi-die architectures. These benefits are especially impactful for AI data center and HPC (high-performance computing) applications, where demand for larger package sizes and higher I/O density continues to accelerate.”

By transitioning from traditional round wafers to rectangular panels, ASE enables greater usable area—up to 96,100 mm² per panel—allowing for more dies per unit and improved material efficiency.

PLP isn’t new. For some time, PTI, Samsung, STMicroelectronics and others have been making packages using PLP. TSMC is expected to enter the PLP field. In addition, Amkor, Innolux, ECHINT, Rapidus and Silicon Box have started developing PLP lines, according to the Yole Group, a research firm.

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At the 2026 IEEE International Symposium on Circuits and Systems (ISCAS) in Shanghai, China’s Huawei described a new design and chip scaling methodology to enable devices at the 1.4nm node and perhaps beyond.

In a keynote, He Tingbo, president of the Semiconductor Business Department of Huawei, described the Tau (τ) Scaling Law, a new principle for guiding the future development of the semiconductor industry. He also serves as chair of the Huawei Scientist Committee.

This concept is designed to circumvent traditional geometric or chip scaling. Using this methodology, Huawei hopes to develop chips with a transistor density that is equivalent to the 1.4nm process node by 2031. The methodology makes use of a technology called LogicFolding.

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Stuck at 7nm

Huawei is a large systems house in China. The company develops and sells a number of systems, including 5G equipment, AI servers, smartphones and other products. For these and other systems, Huawei designs its own leading-edge chips. These chips, in turn, are manufactured using foundry vendors.

Huawei, however, is unable to use TSMC as a foundry, due to a series of export control regulations. So, Huawei has no other choice but to have its chips made by SMIC, China’s largest foundry vendor.

The problem? SMIC is behind in logic technology. For example, TSMC, the world’s largest foundry vendor, is ramping up a new 2nm process using an advanced gate-all-around (GAA) transistor technology. In comparison, SMIC’s most advanced process in production is a 7nm finFET technology. SMIC is developing a 5nm process, with 3nm in R&D.

To make 7nm chips, SMIC is using less advanced equipment, namely 193nm optical lithography systems. It would be easier to manufacture 7nm chips (and below) using extreme ultraviolet (EUV) lithography, a next-generation, 13.5nm wavelength system. ASML, a Dutch-based equipment maker, is the sole supplier of EUV lithography systems in the market.

But China is unable to obtain ASML’s EUV lithography scanners, due to export control regulations. China itself is developing its own EUV lithography systems, but it could take several years to develop these tools. China may never develop EUV.

So, SMIC has no choice but to use less advanced 193nm lithography equipment and other tools to manufacture chips in the fab. With 193nm lithography—along with multi-patterning techniques--chipmakers can manufacture 7nm chips with questionable yields. 5nm is also possible, but there are number of challenges here.

All told, without EUV lithography, China is more or less stuck at the 7nm and/or 6nm node.

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New scaling methods

So, China is exploring new and different ways to circumvent traditional chip scaling. For example, Huawei is devising what it calls the Tau (τ) Scaling Law. Based on this principle, technologies, such as LogicFolding, can be used to compress signal propagation delay and improve transistor density.

This mechanism aims to systematically shorten the time constant τ in order to drive up performance, energy efficiency, and transistor density at each level in the following ways:

*Device level “Optimizing the resistance and parasitic capacitance of transistors and interconnects to minimize the device-level time constant τ at the underlying physical layer,” according to Huawei

*Circuit level “Adopting the LogicFolding architecture to break down the physical boundaries of traditional circuit layouts, significantly shortening critical-path wiring, effectively reducing the resistive and capacitive load of signal propagation, and ultimately boosting transistor density and circuit performance,” according to the company.

*Chip level Employing full-stack coordinated design of software, architecture, and silicon to achieve fine-grained, workload-driven control over instruction and data flows, enhancing system-level parallelism and efficiency, and significantly reducing end-to-end execution time,” according to the company.

*System level “Redefining interconnect protocols for computing systems with UnifiedBus to achieve unified memory addressing and native memory semantics for SuperPoDs, significantly reducing system communications latency,” according to the company.

Over the past six years, Huawei has designed and produced 381 chips based on the τ Scaling Law, serving a wide range of industries, sectors and markets. The company’s Kirin chips scheduled to launch in Fall 2026 will be the first to adopt the LogicFolding architecture, which will enhance chip performance.

By 2031, the high-end chips from the company’s designs based on the τ Scaling Law are expected to feature a transistor density that is equivalent to 14 Å (1.4 nm) processes.

Looking ahead, Huawei’s He said: “We believe that openness and collaboration are key to driving ongoing progress in the semiconductor industry. No single company can independently find all the answers along the path of semiconductor evolution. With the τ Scaling Law, we look forward to working closely with scientists, engineers, and industry partners around the world to drive the sustainable development of the semiconductor and electronics industries.”

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