AlixLabs Demos Novel Pitch Splitting Technology On UMC’s Wafers

The technology promises to pattern chips at 3nm without EUV.

By Mark LaPedus

At the recent 2025 CMC Conference, AlixLabs AB presented its latest findings on the company’s novel pitch splitting technology for use in advanced chip production.

Based on an advanced atomic layer etch (ALE) process, AlixLabs’ technology is said to extend multi-patterning below the 7nm node, even down to 3nm, in the fab. Still in the R&D phase, this technology is positioned as an alternative to traditional multi-patterning techniques as well as extreme ultraviolet (EUV) lithography.

At CMC, AlixLabs demonstrated its technology using 300mm wafers from UMC. The company also recently presented some results using test silicon from Intel.

AlixLabs, a Swedish ALE startup, has developed a semiconductor manufacturing process known as APS (Atomic Layer Etching Pitch Splitting). Used in chip production for many years, ALE is a technology that removes materials in chips at the atomic level.

AlixLabs is using an extreme form of ALE. APS is capable of extending multi-patterning processes at advanced nodes. APS is said to double the fin density in devices without using EUV.

In a recent demonstration, AlixLabs’ APS technology was used to etch structures on test silicon provided by Intel. The technology achieved a 25nm full metal pitch, comparable to a 3nm-class process from leading-edge foundries. It achieved this milestone without using EUV lithography.

This in turn demonstrates that sub-5nm-class patterning is possible just by using APS. “APS proves that there’s no need for complex multi-patterning like SADP and SAQP to produce 5 nanometer chips and beyond. It extends the potential of immersion lithography for use with critical mask layers for even 3-nanometer processes,” said Jonas Sundqvist, chief executive and co-founder of AlixLabs.

In a separate demonstration, AlixLabs’ technology successfully “halved pitch” various structures on UMC’s 300mm wafers. “We are sharing more proof that the APS process can be a game changer for leading foundries. Thanks to UMC, we have been able to verify our process on production wafers that are shipped in quantities measured in millions of wafers annually,” said Robin Athle, principal researcher at AlixLabs. “Our mission is to create equipment that allows companies that don’t have access to EUV tools to scale down their production to 5 nanometer and beyond. By eliminating the dependency on EUV lithography, we are offering the industry a path towards more sustainable and economically feasible high-density chip production.”

UMC expands

In a separate announcement, UMC recently unveiled its new fab facility in Singapore. The first phase of the new facility will start volume production in 2026, bringing UMC’s total production capacity in Singapore to more than 1 million wafers annually.

The new facility will produce chips using UMC’s 22nm and 28nm processes. The facility, a greenfield expansion adjacent to UMC’s existing fab in the Pasir Ris Wafer Fab Park, spans two phases.

Up to $5 billion will be invested to bring the first phase to full capacity of 30,000 wafers per month, with room for further investment in a second phase expansion in the future.