ASE Launches Panel-Level Packaging Line
The Taiwanese OSAT is supporting the 310mm x 310mm panel format
By Mark LaPedus
Taiwan’s Advanced Semiconductor Engineering (ASE), the world’s largest OSAT, has launched an automated 310mm x 310mm panel-level packaging production line.
ASE’s automated panel-level packaging line supports the 310mm x 310mm format. The line is compatible with the company’s advanced packaging platforms, including its FOCoS and FOCoS-Bridge lines, delivering line/space capabilities of 2/2µm and 8/8µm, respectively.
ASE’s FOCoS line is a fan-out package, which is flip-chip mounted on a high pin count ball grid array (BGA) substrate. The FOCoS-Bridge line utilizes tiny silicon pieces with routing layers as in-package interconnect between chiplets.
The new panel line is expected to enter production in the first half of 2027, according to ASE. ASE and other OSATs provide third-party packaging and testing services for the semiconductor industry.
PLP gains steam
ASE is seeing strong demand for its advanced packaging and testing services in the market. The demand is being driven by AI and other technologies. To meet demand, ASE is building or acquiring new facilities. For example, the company is building a new IC test facility in Kaohsiung, a city in southern Taiwan.
ASE and others are also ramping up or developing panel-level packaging (PLP) lines. PLP is a different way to manufacture advanced packages. Typically, in some advanced package types, multiple chips are processed and packaged on round 200mm or 300mm wafers.
In PLP, however, multiple chips are processed on a large rectangular substrate or a panel. PLP allows for more chips to be processed at the same time, thereby increasing the throughput. PLP also reduces manufacturing costs.
“This shift to panel-level packaging addresses critical industry challenges, including rising interposer sizes and declining wafer-level efficiency,” according to ASE. “The larger panel format supports higher throughput and reduced cycle time, while enabling integration of increasingly complex multi-die architectures. These benefits are especially impactful for AI data center and HPC (high-performance computing) applications, where demand for larger package sizes and higher I/O density continues to accelerate.”
By transitioning from traditional round wafers to rectangular panels, ASE enables greater usable area—up to 96,100 mm² per panel—allowing for more dies per unit and improved material efficiency.
PLP isn’t new. For some time, PTI, Samsung, STMicroelectronics and others have been making packages using PLP. TSMC is expected to enter the PLP field. In addition, Amkor, Innolux, ECHINT, Rapidus and Silicon Box have started developing PLP lines, according to the Yole Group, a research firm.