Challenges And Opportunities In Advanced Packaging

The CTO of a new company called Qnity talks about advanced packaging, chiplets, bump pitch scaling, hybrid bonding and other topics

By Mark LaPedus

Randal King, chief technology officer at Qnity Electronics, sat down with Semiecosystem to talk about Qnity and the company’s charter. King also talked about Moore’s Law, IC packaging, chiplets, bump pitch scaling and hybrid bonding.

Prior to Qnity, King was vice president of R&D, Electronics and Industrial at DuPont. Last year, DuPont announced a plan to spin-off its Electronics and other business units. In April 2025, DuPont announced that “Qnity Electronics” is the name of the planned independent electronics public company that will be created through the intended spin-off of its Electronics business.

Semiecosystem: Who is Qnity and what is the company’s charter? What markets and technologies are your primary focus?

King: DuPont is targeting Nov. 1, 2025, for the completion of its spin-off of the Electronics business, to be called Qnity. Qnity is pushing the boundaries of what’s possible in the electronics world—whether that’s improving chip performance, boosting signal integrity, managing heat, or helping devices get smaller and more energy efficient.

We’re hitting the ground running as one of the largest pure-play electronics companies with a legacy spanning more than 50 years, 10,000 employees globally, nearly 40 manufacturing sites, and nearly 20 R&D facilities. Qnity will be a global leader in differentiated electronic materials, supplying key consumables used in semiconductor chip manufacturing, advanced electronic materials for packaging and interconnects, thermal management and innovative assembly and display technologies.

Semiecosystem: Let’s talk about Moore’s Law and chip scaling. At present, leading-edge foundry vendors are readying their 2nm or 1.8nm processes. More advanced processes are in R&D. Thanks to the advancements in process technology, several companies are developing chips at the 2nm node and beyond. Yet, we hear that traditional chip scaling is slowing and becoming more difficult at each node. What’s happening with traditional chip scaling and/or Moore’s Law?

King: Moore’s Law isn’t dead, but it’s in the slow lane. We’re no longer doubling transistor density every two years while lowering costs; now, it’s more like every three years stretching to five years, and the cost of progress is rising sharply. At sub-2nm, manufacturing yields are increasingly difficult to maintain, and managing heat and power remains a major roadblock. Imagine a fleet of ultra-fast supercars (advanced chips) stuck in a two-lane parking lot. The chips are ready, but the infrastructure hasn’t kept up. This bottleneck leads to staggering inefficiencies, with up to 30% of potential computing power wasted.

That’s why advanced packaging is such a required breakthrough—it’s the pit crew that gets those supercars back on track. Companies are doubling down on this approach. At this year’s IEEE IEDM, TSMC unveiled a roadmap to 2030 that includes packing up to a trillion transistors into a single chip package using 3D-stacked chiplets. While today's densest monolithic dies top out at 146 billion transistors (as seen in AMD’s MI300), TSMC’s A10 node is expected to reach a milestone of 200 billion transistors per die. To bridge the gap to 1 trillion, the key will be high-efficiency communication between logic and memory chiplets, mimicking the behavior of one massive processor. In short, Moore’s Law isn’t over. It’s being reinvented through packaging innovation and architectural creativity.

Semiecosystem: IC packaging is not new and has been around for decades. An IC package is a product that encapsulates a chip and protects it from harsh operating conditions in the field. In recent times, advanced packaging has become a more significant part of the semiconductor industry. Why? And what role does advanced packaging play now?

King: Advanced packaging is no longer just about protecting chips—it’s now central to pushing the limits of performance, efficiency, and density, as I previously mentioned. As transistors shrink and chip complexity increases, traditional ways of mounting chips on circuit boards can’t keep up. Today’s chips, some with over 30 miles of copper wiring, need faster and more direct pathways for data. Advanced packaging enables tight 3D stacking and chiplet integration, which improves communication speed and reduces power consumption. TSMC’s SoIC technology and roadmap toward A10 packaging are perfect examples, supporting high-performance computing and AI workloads with precision interconnects and thermal control.

However, performance gains come with new challenges: these chips can now compute faster than data can move on or off the die. In AI and data center environments, bottlenecks between memory and logic lead to massive power inefficiencies. These inefficiencies happen not only in computation, but also in the energy spent cooling overheated systems. This is why packaging has become a system-level concern.

AMD noted at ECTC that the ‘power wall’ could push data center electricity usage to 10% of the U.S.’s electrical output by 2030. The answer lies in smarter packaging design, including photonic chips and co-packaged optics, accelerating bandwidth while reducing heat, enabling tomorrow’s computing without draining the energy bank.

Semiecosystem: There is a lot of talk about chiplets these days. In chiplets, you take different dies, or chiplets, and then assemble them in a package, creating a new chip design. Chiplets are promising, but there are some challenges here. Any thoughts about chiplets and the challenges?

King: Chiplets hold great promise for building more powerful, flexible, and cost-effective systems by enabling heterogeneous integration. In other words, combining cutting-edge logic cores with older, specialized dies delivers power, provides data storage and security, and enables RF capabilities. This approach allows designers to mix and match technologies and utilize mature fabrication processes where appropriate, helping to control costs while maximizing performance. But while the concept is powerful, the execution is complex. The term ‘chiplet’ itself is inconsistently defined. Sometimes it refers to 2D side-by-side assemblies, and other times it includes full 3D stacking, leading to industry confusion. This lack of standardization complicates design, manufacturing, and supply chain integration.

Efforts like the Universal Chiplet Interconnect Express (UCIe) aim to bring much-needed consistency and interoperability to chiplet-based systems. Still, there's more work to develop standards for emerging technologies like co-packaged optics. Ultimately, unlocking the full potential of chiplets will require engineering ingenuity and industry-wide collaboration.

Semiecosystem: AI is a hot topic. In many cases, AI chips are incorporated in 2.5D and related packages. The chips in these packages are stacked and connected using traditional copper microbumps. The most advanced bumps are structures with 40μm to 36μm pitches. What are the challenges to produce smaller bumps at finer pitches, say down to 10μm? Do we need new breakthroughs in bump pitch scaling?

King: Right now, the most advanced copper microbump structures use pitches as tight as 36μm, and the industry is pushing toward 20μm–25μm using solder-capped micropillars very soon. Early R&D is already underway to evaluate interconnects at 10μm pitch, but getting there won’t be easy. As the pitch gets tighter, there’s less space available to form reliable joints. Ensuring everything lines up perfectly (coplanarity) presents a significant challenge. Overlay accuracy between bumps on opposing surfaces will have to advance and keep up with I/O pitches.

You also start seeing issues like solder bridging and increased intermetallic compound (IMC) formation, which can affect reliability. The smaller the joint, the higher the proportion of brittle IMCs. Right now, nickel is commonly used as a barrier to control copper diffusion. However, it's not ideal at these ultra-fine scales. So researchers are exploring other materials. To make 10μm work, we’ll need more than just tweaks. We’ll need breakthroughs in barrier layers, solder processes, and bonding techniques.

Semiecosystem: Beyond a certain pitch, you need hybrid bonding. Hybrid bonding connects chips using direct copper-to-copper bonds. For years, hybrid bonding has been used for CMOS image sensors. Now, we are seeing hybrid bonding in other markets, such as 3D NAND and advanced packaging. What’s next for hybrid bonding? What are the benefits of hybrid bonding and some of the challenges?

King: Hybrid bonding is quickly becoming one of the most important breakthroughs in advanced memory and chip packaging. Instead of using traditional microbumps, it connects chips directly (copper-to-copper), which means faster data transfer and better power efficiency for applications like HBM (high bandwidth memory).

As HBM designs push toward stacking more than 16 DRAM dies, traditional approaches hit physical limits, even with ultra-thin dies. Hybrid bonding helps bypass that by creating a thinner, solder-free stack and enabling super-fine I/O pitches below 10μm. That’s something today’s methods can’t do.

We also see momentum building around die-to-wafer hybrid bonding for advanced node packaging. That brings challenges: it’s extremely sensitive to particles, the copper surfaces must be perfectly flat, and everything must bond at low temperatures. One promising solution is grain-engineered copper, which could make low-temp bonding more practical at finer pitches. Fully 3D-stacked DRAM is still a few years away, but hybrid bonding is already helping us overcome the interconnect hurdles that previously slowed us down. Hybrid bonding is key to keeping pace with AI, big data, and the next wave of compute demands.

Semiecosystem: Hybrid bonding requires several processes, including various planarization steps using chemical mechanical polishing (CMP). What are some of the issues and challenges here? Any solutions here?

King: With hybrid bonding, you’re dealing with dielectric and metal surfaces simultaneously, so getting them perfectly flat and aligned is no small task. That’s where advanced chemical mechanical polishing (CMP) comes in—it’s essential for achieving the coplanarity necessary for a clean, reliable bond. Ultra-flat, ultra-clean surfaces with incredibly low defect levels and minimal scratches are crucial to success.

You also need tight control over how much material you remove on metal and dielectric layers. To meet those demands, a lot of innovation is happening in CMP pads, slurries, and even the materials used for copper and dielectric layers. Our latest CMP consumables, such as pads, slurries, and cleaning solutions, are already being used in hybrid bonding applications, and we’re seeing real breakthroughs. We’re working closely with chipmakers to fine-tune performance and push the boundaries even further.

Semiecosystem: What’s next for Qnity?

King: DuPont is targeting Nov. 1, 2025, for the completion of its spin-off of the Electronics business, to be called Qnity. Qnity will be one of the largest global leaders in electronic materials and solutions for the semiconductor and advanced electronics industries. As the partner of choice for our customers today, we have a seat at the design table working to advance their technology roadmaps through materials science and engineering solutions that the next generation of advanced computing and connectivity applications require. We bring a unique, end-to-end perspective on the electronics value chain, and we’re excited about what’s next.