Chiplet Consortium Releases New Spec
The Universal Chiplet Interconnect Express (UCIe) Consortium has released the UCIe 3.0 specification
By Mark LaPedus
The Universal Chiplet Interconnect Express (UCIe) Consortium has released the UCIe 3.0 specification, marking the next stage in the evolution of an open chiplet standard.
The specification delivers new performance enhancements for chiplets, which is a way to develop next-generation chip designs. Basically, chiplets are small modular dies or chips, which have a specific function. The dies, or chiplets, are connected and then combined in a package, creating a completely new and more complex chip design. This approach is a fast and low-cost way to develop complex chips, but there are several challenges to develop them.
For example, in a chiplet-based design, the individual chiplets must communicate with each other. Typically, semiconductor vendors tend to use proprietary die-to-die communication protocols and interfaces. Larger companies can afford to develop proprietary die-to-die technologies. Most vendors don’t have the resources.
Fortunately, the semiconductor industry is developing standard die-to-die technologies for chiplets. The idea is to allow more companies to adopt the chiplets concept using open standards.
In 2022, several companies banded together and announced the UCIe Consortium. This group is developing various specifications, which cover a standard die-to-die I/O physical layer, die-to-die protocols, and software stacks.
Now, the UCIe Consortium, the open standard for interconnects between chiplets within a package, announced the release of the UCIe 3.0 specification. Here are the specification highlights for UCIe 3.0:
*Support for 48 GT/s and 64 GT/s data rates, doubling the bandwidth of UCIe 2.0 (32 GT/s) to meet high-performance chiplet demands
*Runtime recalibration enhancements enable power-efficient link tuning during operation by reusing initialization states
*Extended sideband channel reaching up to 100mm supports more flexible SiP topologies
*Support for continuous transmission protocols through mappings, enabling uninterrupted data flow in Raw Mode for new applications such as connectivity between SoC and DSP chiplets
*Early firmware download standardization using Management Transport Protocol (MTP) for streamlined initialization
*Priority sideband packets allow deterministic, low-latency signaling for time-sensitive system events
*Fast throttle and emergency shutdown mechanisms provide immediate system-wide notifications via open-drain I/O
*Fully backward compatible with all previous UCIe specifications for seamless integration and adoption
“UCIe 3.0 represents a critical step forward for the chiplet industry, delivering the speed, efficiency, and manageability needed to scale multi-chip designs,” said Cheolmin Park, president of the UCIe Consortium and corporate vice president of Samsung Electro-Mechanics. “With increased data rates and extended manageability capabilities, the next generation of UCIe technology will empower developers to build more flexible, interoperable, and high-performance SiP solutions as we all work together to build a truly open and interoperable chiplet ecosystem.”
The UCIe 3.0 Specification is available to the public by request here.