CMP Challenges Seen For 200mm, Silicon Carbide

Axus Technology outlines the challenges with chemical mechanical planarization (CMP) processes for chips, 200mm fabs and silicon carbide (SiC) devices.

By Mark LaPedus

Dan Trojan, president and chief executive of Axus Technology, sat down with Semiecosystem to discuss the challenges with chemical mechanical planarization (CMP) processes in the semiconductor industry, especially for 200mm fabs and SiC devices. Axus Technology provides CMP foundry services and tools.       

Semiecosystem: Can you tell us about Axus Technology and the company’s charter?

Trojan: Axus Technology is a global OEM company based in Chandler, Arizona, bringing the latest surface processing solutions to emerging technology industries such as semiconductor, MEMS, automotive, defense and aerospace, life sciences, and IoT since 2002. We provide advanced CMP tools and technology, along with technical expertise for polishing, wafer cleaning, precision wafer grind processing and legacy tools.

We offer our clients three branches of support: equipment (new, remanufactured, refurbished); a development lab; and parts and services. Our operations include a production floor for new, advanced CMP tools and remanufactured legacy processing tools, a fully equipped Class 100 foundry cleanroom for development and foundry processing, and a worldwide parts and services department for existing equipment.

At Axus Technology, our process development team is here to facilitate the need for advances in wafer technology and efficient wafer production with new designs and novel applications. We implement turnkey solutions for process development, foundry processing, and equipment tooling, including tool installation and training, field service, and consumable selection.

Semiecosystem: Can you describe CMP and why this technology is important?

Trojan: CMP, or chemical mechanical planarization, is a critical process in the semiconductor industry that ensures the planarity and smoothness of surfaces on semiconductor wafers. It involves a combination of chemical and mechanical processes to achieve the desired surface characteristics. The importance of CMP lies in its ability to create the precise and uniform surfaces necessary for the fabrication of integrated circuits and other semiconductor devices.

Semiecosystem: As chip complexity increases at advanced nodes, I believe you need more CMP steps. Would you agree that is the case?

Trojan: As chip complexity increases at smaller process nodes, the need for more CMP steps may indeed arise. This is due to the intricate nature of advanced semiconductor designs, which often involve multiple layers and intricate structures. The smaller feature sizes and increased layer counts in advanced nodes can lead to greater challenges in achieving the required planarity and uniformity on the wafer surfaces. As a result, additional CMP steps may be necessary to address these complexities and ensure the desired surface characteristics.

In advanced semiconductor manufacturing, CMP plays a crucial role in achieving the precise planarity and surface smoothness required for intricate device structures. As the complexity of chip designs increases, the importance of CMP in achieving uniform and defect-free surfaces becomes even more critical.

Semiecosystem: Axus Technology is selling a CMP tool for the 150mm/200mm fab market, right? Can you briefly describe the Capstone System?

Trojan: The new Capstone CS200 series is the next-generation CMP processing tool from Axus Technology, offering wafer polishing performance for 100mm, 150mm, and 200mm wafer sizes. The system architecture includes a load-polish-unload sequence for high throughput process capability and reduced system footprint. Capstone provides more efficient application and utilization of chemical mechanical polishing slurry, offering a 40% to 50% reduction in slurry consumption. The unique pad conditioning system also provides up to double the pad life of other CMP tools. The Capstone CS200 series is the wafer processing equipment of the future and brings significant reduction in cost of ownership, substantially reducing overall CMP process costs.

The Capstone CMP system, coupled with our Crystal wafer carrier specifically designed for fragile wafer handling and advanced profile control, delivers premium-quality silicon carbide (SiC) substrates with sub-micron TTV and a sub-Angstrom surface finish.

The new Capstone CS200 series is the next-generation CMP processing tool from Axus Technology. Source: Company

Semiecosystem: The 150mm/200mm fab markets are rather mature. Why does the industry need a CMP tool for these types of fabs?

Trojan: 200mm CMP tools being used in the industry today were brought to the market in the mid-1990s, meaning their design and technology content are nearly 30 years old. As the pace of technology development has been so rapid and extensive during this period, these products clearly lack the leading-edge capability and functionality that our industry demands. Many 200mm fabs now recognize the need to upgrade their existing installed base of legacy CMP tools to address the ongoing challenges of continuing to rely on legacy/obsolete toolsets.

Many of the emerging and most compelling technology trends in our industry today either rely on or are limited to 200mm and smaller substrate sizes. Examples of this include microLED, MEMS and compound semiconductor materials for power devices such as SiC and gallium nitride (GaN). Many of these materials will likely never scale above 200mm due to material properties or other physical limitations. These considerations further highlight the need for advanced 200mm CMP systems in today’s marketplace.

Semiecosystem: 200mm fabs have been around for a long time. These fabs are still viable and will remain in production for a long time. I believe there are some new 200mm fabs on the drawing board. Yet, it’s difficult to find new or used tools for 200mm fabs. Any thoughts about the future of 200mm fabs and the availability of 200mm equipment?

Trojan: As mentioned above, 200mm fabs will always be needed in our industry. It’s worth noting that as substrate sizes have continually increased over time, from 100mm to 125mm to 150mm to 200mm and now 300mm, the industry migrated to the newest and largest substrate size and never looked back. However, beginning in 2018, 200mm substrates and supporting process equipment had a strong resurgence in demand, which still continues today. Most likely, equipment suppliers will continue to address this demand either by bringing new 200mm platforms to the market, or by restoring their ability to build new, often updated, versions of legacy 200mm tools.

Semiecosystem: I believe you are seeing a demand for your CMP tools in the SiC device market. What are the CMP challenges associated with SiC?

Trojan: High material hardness causes low material removal rates, high process cost-of-ownership, and low system throughput. Also, SiC wafers are thin and very fragile, which can lead to high wafer breakage rates, low overall yield, and higher equipment downtime. Substrates require polishing of both sides, not just the device or front side as is typical for nearly all other CMP applications. The pre-epitaxy surface quality requires integrated post-CMP cleaning, which is significantly more difficult given the handling challenges associated with SiC.

Semiecosystem: What about the cost-of-ownership for CMP in the SiC device market? Are the costs high?

Trojan: The cost-of-ownership for SiC CMP is much higher than for other CMP applications due to a number of factors, as listed below:

*High material hardness and double-sided polishing requirement result in long polishing times, which in turn increases slurry consumption and associated waste volume and treatment costs, while reducing polish pad life and system throughput.

*Low system throughput drives up capex costs and cleanroom space requirements.

*Lack of maturity and competition among SiC CMP consumables suppliers contribute to less favorable economics relative to consumables costs.

Semiecosystems: Today, the vast majority of SiC devices are manufactured in 150mm fabs. Some SiC device vendors are making the transition to 200mm fabs. What are the challenges here?

Trojan: SiC device makers have faced challenges with yields and defect levels during the transition from 150mm to 200mm wafers. Some vendors are still struggling with their yield and defect levels at 150mm, indicating the complexity of maintaining high yields and low defect levels during the transition. The transition to 200mm fabs requires significant retooling and improvement in infrastructure, which comes with exponential costs. This includes the need for specialized equipment and infrastructure improvements to support the larger wafer size, such as SiC epitaxial chemical vapor deposition (CVD) performed at high temperatures not used for silicon.

SiC material processing poses challenges due to its density and hardness. Injecting, accurately placing, and activating dopants without damaging the crystal lattice is a significant challenge, as it can reduce performance and power efficiency. Specialized equipment and processes are required to address these concerns.

The availability of equipment also remains a challenge, with lead time for wafer fab and test equipment being a significant concern. This indicates potential supply chain issues and the need for efficient equipment procurement to support the transition.