Foundryecosystem Report: Huawei, Terafab, EU, GF, AMAT
How will Huawei make 1.4nm chips? Plus: Terafab's fuzzy logic, EU Chips Act 2.0, GF deals, Applied expands, JCET goes 3D
By Mark LaPedus
The foundry industry is an important part of the semiconductor business. IC packaging is also important.
Nearly every week, there are several new and major announcements in the semiconductor foundry and packaging markets.
To help the industry, Semiecosystem has released the latest edition of “The Foundryecosystem Report.” This report provides a snapshot of the latest announcements in the foundry and packaging markets. (The report is free for readers.) Here’s what this report covers:
1—China’s Huawei plans to develop 1.4nm chips using the Tau (τ) Scaling Law and LogicFolding. What does that all mean? TechInsights weighs in.
2—Does the math add up for Musk’s Terafab project?
3—The EU rolls out Chips Act 2.0.
4—GlobalFoundries announces several deals.
5—Applied Materials expands in Singapore.
6—JCET expands into 3D integration.
7—UCLA unveils a new semi hub.
8—Global chip sales grew in Q1 (memory vs non-memory).
Huawei’s ambitious plans
At a recent event, He Tingbo, president of the Semiconductor Business Department at China’s Huawei, described a methodology to develop chips at the 1.4nm node and perhaps beyond.
This methodology centers around two key concepts--the Tau (τ) Scaling Law and LogicFolding. Both concepts are designed to circumvent traditional geometric or chip scaling. Using these methodologies, Huawei hopes to develop chips with a transistor density that is equivalent to the 1.4nm process node by 2031.
Huawei’s presentation, however, raised more questions than answers. What is the Tau (τ) Scaling Law? What is LogicFolding? And how can Huawei develop chips at the 1.4nm node by using these concepts?
Before answering these questions, let’s briefly look at the challenges facing Huawei and others in China in terms of advanced semiconductor technology. First, Huawei designs its own leading-edge chips. But the company is unable to use TSMC as a leading-edge foundry vendor, due to a series of complex export control regulations.
So, Huawei has no other choice but to have its chips made by SMIC, China’s largest foundry vendor. Yet, SMIC’s most advanced process in production is a 7nm finFET technology. In R&D, SMIC is developing a 5nm process.
All told, SMIC--and China as a whole--are stuck at the 7nm and/or 5nm node.
To develop chips beyond the 5nm node, SMIC would need more advanced semiconductor manufacturing equipment. Simply put, the company requires ASML’s extreme ultraviolet (EUV) lithography systems. The problem? China is unable to obtain ASML’s EUV lithography scanners, due to export control regulations.
So, how can China circumvent the traditional methods of making leading-edge chips? To answer that question, I reached out to Dan Hutcheson, vice chair at TechInsights, a market research firm. In an e-mail exchange, here’s what Hutcheson said:
Semiecosystem: What exactly is Tau Scaling?
Hutcheson: Tau Scaling is simply a shift from geometric scaling to temporal scaling (τ). It takes you back to the 60s and 70s, because Moore’s Law was about geometric scaling, which doubled transistors for roughly the same areal cost, hence cutting the cost of a transistor. In contrast, Dennard’s Scaling Laws were a combination of temporal and power scaling. He pointed out that shrinking transistors puts them closer together, so they operate faster and use less power. What He Tingbo was essentially saying is that there are alternatives to shrinking to making chips faster. At its core, there is little new here, or as I wrote in The Chip Insider, ‘Huawei has just learned Electrical Engineering and now wants to teach the world.’
Semiecosystem: What is LogicFolding? Does it resemble TSMC’s SoIC technology (i.e. 3D heterogeneous integration, chiplets and hybrid bonding)?
Hutcheson: As a substitute for Moore’s Law scaling, LogicFolding uses heterogeneous integration (HI) to move critical blocks of transistors closer to each other by stacking them on top of each other. Again, nothing new here conceptually, but really new in branding and execution. At an execution level, Western approaches to HI have mostly been to shrink what used to be board-level integration down into a single package of chiplets. SoC designs are still done on a 2D plane. LogicFolding’s significant difference is designing the SoC with its critical timing paths on a 3D plane. As I wrote in The Chip Insider, chip stacking is already used in HBM. It’s less common for logic because of thermal issues. So, He’s Tau Scaling and LogicFolding concepts are definitely feasible and may deliver a good enough solution, but not best in class with older node technology.
Semiecosystem: Does Huawei’s technology somehow change the game? In other words, will it allow the company to play catch-up in logic scaling? Or is it much ado about nothing?
Hutcheson: He Tingbo’s LogicFolding concept is a wake-up call to Western EDA players, who have been moving in this direction, but at a slower pace. I’ve been writing about the need for HI since 2015 and I’m not the only one. But the arrival of EUV and renewed pace in shrinking allowed the West to pullover into an innovation rest stop. Restricting access to EUV and leading-edge chips forced Huawei to stay on the innovation fast lane. They have yet to pass us, but they will if we don’t get back into the fast lane.
Fuzzy logic
Meanwhile, Elon Musk recently announced plans to build a new and giant fab. As reported, the fab project, called the Terafab, is a joint effort between Tesla and SpaceX. Musk’s goal is to build a large semiconductor fab in Austin, Texas--at a cost of $20 billion to $25 billion. A fab is a large facility used to manufacture chips.
The proposed Terafab is expected to manufacture both logic and memory chips all in the same facility. Initially, the goal is to produce logic chips at the sub-2nm node. And if that isn’t enough, the same facility will also package and test these chips.
Intel will apparently become a manufacturing and packaging partner for the Terafab project. Intel’s 14A process technology will play a big role in the project.
On its website, Tesla has several job postings for the Terafab. Musk has apparently talked to equipment vendors about obtaining tools for the fab.
All of this sounds exciting, right? A new U.S. fab with plenty of high-paying jobs!
The problem? Musk’s ambitious fab plans still appear to be unrealistic. The math simply doesn’t add up, at least according to one analyst.
In a new research note, an analyst from TD Cowen crunched various numbers based on Musk’s Terafab projections. This was billed as a “thought experiment,” not a definitive forecast. Here’s what the raw numbers say:
“SpaceX’/TSLA’s goal is to build a semiconductor facility spanning logic, memory, and packaging, ultimately capable of producing up to 1 TW per year of AI compute (~50x this year’s industry deployment). That is obviously far beyond anything the industry is deploying today, which is why we think the right way to look at it is as a ceiling thought experiment, not a base-case forecast,” said Krish Sankar, an analyst at TD Cowen, in the research note.
“Based on our 1 GW framework, we estimate that 1 TW would be equivalent to roughly 6M NVL72s of Vera Rubin, requiring ~3.5M wspm of front-end wafer capacity for GPUs/CPUs and ~10M wspm of HBM. We estimate that meeting that goal would require ~$1.5T of WFE (wafer fab equipment),” Sankar said.
“More broadly, our work suggests that a scaled version of Terafab could require ~950 litho tools (~200 High-NA, ~150 low-NA, and ~600 DUV), assuming each High-NA replaces roughly three low-NA layers,” Sankar said.
None of these figures are realistic. Not even close. Even the near-term goals seem unrealistic. “Near term, it has been reported that SpaceX intends to invest $55B in Grimes County, Texas as part of the initial buildout. Based on our fab cost breakdown, we estimate that could translate into ~ $35B of construction spend and $20B of WFE over 2028–29. Assuming a 50/50 split across logic/DRAM, it could imply 50K wpm of logic capacity and ~100K wpm of DRAM,” Sankar said.
All told, Musk may end up building the Terafab. But it won’t be as majestic as previously thought. The Terafab may turn out to be something different than what Musk is talking about.
Botton line: Get a more realistic picture of the Terafab before you accept any equipment orders or get a high-paying job offer. The Terafab may prove to be a lucrative endeavor. Find out if it’s for real or not.
EU Chips Act 2.0
The European Commission (EU) has released its proposals for the new European Chips Act 2.0. The proposals introduce new measures to further boost the semiconductor industry in the European Union (EU). It hopes to reduce strategic dependencies and support advanced chip production in the EU.
“The EU remains dependent on third countries in key areas such as advanced chip manufacturing or semiconductor design,” according to the EC. “Securing a stable chips supply is necessary to ensure that critical infrastructures and technologies remain secure, resilient and aligned with European values.”
The Chips Act 2.0 builds on the progress made by the original Chips Act and will both reinforce current European strengths and build capacity in cutting-edge semiconductor technologies.
You can download the full regulation proposal, the annexes, the impact assessment and a summary of this impact assessment here .
GF deals
GlobalFoundries (GF), a U.S.-based foundry vendor, has made several announcements in recent times, including:
*GF has announced a strategic partnership with the U.S. Department of Energy’s Genesis Mission, the department’s initiative to accelerate scientific discovery through artificial intelligence and advanced computing.
*Sivers Semiconductors recently announced a strategic collaboration with GF to develop advanced silicon photonics solutions for the high-growth AI infrastructure market. Sivers Semiconductors’ laser arrays will be integrated into reference designs built on GF’s silicon photonics platform. The collaboration supports a range of optical connectivity architectures, including co-packaged optics (CPO), linear pluggable optics (LPO), and other emerging data center interconnect solutions. Sivers’ laser arrays will also be available in GF’s Silicon Photonics Co-packaged Advanced Light Engine (SCALE) platform for next-generation optical sub-assemblies and light engine architectures.
*GF has completed its previously-announced acquisition of Synopsys’ ARC Processor IP Solutions business. GF’s recent acquisition of MIPS, combined with ARC, brings together RISC-V processor IP, software tools, custom design and advanced manufacturing into a single offering.
*CEA‑Leti reaffirmed its collaboration with GF in the FAMES Pilot Line. GF continues to work on FD-SOI technology in the pilot line. The FAMES Pilot Line is designed to accelerate early‑stage research and development in advanced semiconductor technologies. CEA-Leti is the coordinator of the pilot line. Separately, CEA-Leti recently announced a major milestone in the evolution of 3D integration for high-performance computing (HPC), advanced smart-vision systems and artificial intelligence (AI), demonstrating a functional test vehicle utilizing die-to-wafer (D2W) hybrid bonding with pitches down to 1μm.
Applied expands in Singapore
Applied Materials has expanded its manufacturing and R&D operations in Singapore.
Applied’s new US$500 million (S$600 million) Tampines Campus more than doubles the company’s advanced cleanroom capacity in Singapore. The new facility is already operating at volume production, according to Applied, a Santa Clara, Calif.-based supplier of fab equipment.
The facility expands the company’s global fab equipment manufacturing footprint, which also includes facilities in the United States, Europe, Israel and Taiwan.
Singapore 2030 plan
Over the past several years, Applied has nearly doubled its global manufacturing capacity.
Singapore is a major manufacturing center for Applied. In 2022, the company announced its “Singapore 2030” initiative—a multi-faceted plan to expand its operations in Singapore over the next eight years. The plan is targeted at strengthening the company’s global manufacturing and R&D capabilities, broadening its ecosystem partnerships in Singapore and promoting local workforce development.
Today, the Singapore campus features a large manufacturing cleanroom and production capacity along with R&D facilities. With the expansion, Applied anticipates adding approximately 1,000 new local jobs over the next few years.
Applied is also building a new R&D center in the United States. In recent times, Applied has announced several R&D partnerships for its R&D facility, dubbed the EPIC Center. Broadcom and SCREEN Semiconductor Solutions are the latest partners in the EPIC Center.
JCET expands
JCET, China’s largest OSAT, has opened its new facility for high-density 3D system integration at its Jiangyin manufacturing base.
The new facility represents a big step in JCET’s ongoing expansion of advanced packaging capacity. The facility includes 7,000 square meters of cleanroom space and is expected to achieve production line readiness by the end of this month. It will provide advanced packaging technologies and services for applications such as power modules for AI data centers.
In a separate move, JCET launched its next-generation high-density 3D power module packaging and test solutions designed for AI data center applications. Built on JCET’s XDPKG-3DSiP (3D system-in-package) technology, the new solution integrates high-density multilayer interconnects with a three-dimensional module architecture to optimize power devices, passive components, interconnect structures and thermal paths within a compact package footprint.
AI semi hub
Broadcom, Applied Materials, GlobalFoundries, Meta and Synopsys are partnering with the UCLA Samueli School of Engineering to establish a $125 million Semiconductor Hub aimed at accelerating research and workforce development in AI–powered chip technologies. The Semiconductor Hub will be based at UCLA. The initial five-year commitment will establish a long-term collaboration across the semiconductor ecosystem, spanning chip design, software, manufacturing, equipment and advanced materials.
Semi growth in Q1
In total, semiconductor revenues grew 27% in 1Q26 from 4Q25 to reach $319 billion, according to Omdia, a research firm.
Memory revenue drove the increase, rising over 80% sequentially in 1Q26 from 4Q25, according to the research firm. “Removing memory IC revenue shows that the 1Q26 semiconductor market grew, but much more modestly. Non-memory semiconductor revenue grew just over 2% QoQ in 1Q26,” according to Omdia.
“Historically, revenue for both the overall semiconductor market and the non-memory portion declines in Q1 by approximately 4%. Some components performed at typical seasonal rates; Microcontrollers (MCUs), discretes, and optical markets saw slight to mid-single digit QoQ declines for the first quarter of the year. However, other components, especially those in the AI and data center ecosystem, outperformed the typical decline in revenue in the first quarter. This gave the non-memory side of the semiconductor market modest growth,” according to the firm.