Foundryecosystem Report: Terafab; capacity, EUV, GaN
How much does a fab cost? What is the current foundry capacity situation? And why won't TSMC use high-NA EUV?
By Mark LaPedus
The foundry industry is an important part of the semiconductor business. Nearly every week, there are several new and major announcements in the foundry business.
To help the industry, Semiecosystem has released the latest edition of “The Foundryecosystem Report.” This report provides a snapshot of the latest announcements in the foundry and other chip segments. (The report is free for readers.) Here’s what this report covers:
1—How much will Elon Musk’s fab cost?
2—Worldwide chip and packaging capacity are in short supply.
3—Why won’t TSMC use high-NA EUV?
4—Here comes a new interposer supplier.
5—India announces new GaN fab and packaging plant.
6—Who won the GaN legal battle between Infineon vs Innoscience?
7—Chip sales are on record pace.
Terafab costs
How much does a new leading-edge fab cost? The popular answer: $20 billion. Try again. How about $55 billion or more!
Elon Musk recently announced plans to build a new and giant semiconductor fab in Texas. As reported, the fab project, called the Terafab, is a joint effort between Tesla and SpaceX. In addition, Intel is joining the fab project.
Much has been written about the controversial Terafab. Here’s the latest: The estimated capital investment for the initial phases of the Terafab project is $55 billion, with an estimated total capital investment (if additional phases are constructed) of $119 billion, according to a filing by SpaceX.
On June 3, the Commissioners Court of Grimes County, Texas, will convene in a public session that will consider the approval of a property tax abatement agreement for the Terafab.
Chip, packaging capacity shortages
AI chip demand continues to grow at a rapid pace. Many AI chip suppliers are fabless semiconductor companies. In other words, AI chip suppliers use foundry vendors to manufacture their chips.
The problem? There is a shortage of foundry capacity at leading-edge process nodes. There is also a shortfall of select advanced packaging capacity in the global market. And mature-node foundry capacity will soon become tight.
Let’s briefly look at each of these segments.
*3nm and 2nm foundry capacity
Intel, Samsung and TSMC are currently ramping up their respective 2nm-class processes. 2nm represents the most advanced process technology in the market. The 2nm market is still in the early stages.
Meanwhile, for some time, foundry vendors have offered 3nm processes. 3nm appears to be the sweet spot for today’s leading-edge chips. In fact, there are acute shortages of 3nm foundry capacity in the market.
AI chips migrated from the 4nm process node to the 3nm node between late 2025 and 2026, according to TrendForce, a research firm. At the same time, high-end smartphone and PC processors have yet to migrate “en masse” to the next-generation 2nm node, according to TrendForce.
This in turn has resulted in a concentration of demand at the 3nm node. “3nm advanced process capacity—currently dominated by TSMC—has become even more constrained, turning into a scarce resource fiercely contested by global tech giants,” according to TrendForce.
AMD, Apple, Broadcom, Nvidia and other foundry customers are scrambling to obtain more 3nm fab capacity from TSMC. For example, Apple recently reported robust financial results for the quarter. Demand was strong for Apple’s new iPhone 17. That phone incorporates a 3nm system-on-a-chip (SoC), which handles the processing functions. The SoC is manufactured using TSMC’s 3nm process.
The problem? “(Apple) management characterized the iPhone 17 launch through March as strong,” said John Vinh, an analyst with KeyBanc Capital Markets, in a new research note. “Supply remained constrained in the quarter, with the bottleneck primarily being the leading-edge node (TSMC 3nm) used for iPhone SoCs and not memory. In F3Q (June), supply constraints are expected to shift predominantly to the Mac (Mac mini, Studio, Neo).”
TSMC is accelerating the construction of new 3nm fabs to meet demand. “From a supply perspective, Samsung and Intel remain behind TSMC in 3nm foundry progress. Combined with the fact that most chip designs are finalized one to three years in advance, this has led to a temporary single-supplier dynamic dominated by TSMC,” according to TrendForce.
Mature node foundry trends
According to TrendForce, here are the latest trends in the mature-node foundry segments:
*The average 200mm capacity utilization rate among the world’s top 10 foundries is projected to approach 90% in 2026, and remain above 80% through the first half of 2027, according to TrendForce. Several foundry vendors have raised their prices in the 200mm arena.
*“On the 12-inch mature-node side, nearly 70% of capacity expansion is being driven by Chinese foundries, while expansion in other regions remains relatively moderate,” according to TrendForce.
*“TSMC’s planned reduction in 12-inch mature-node capacity may further drive order redistribution, creating opportunities for Tier 2 foundries to raise prices,” according to TrendForce.
What about advanced packaging?
Several years ago, TSMC developed a 2.5D advanced packaging technology called Chip on Wafer on Substrate (CoWoS). CoWoS is used to assemble several different and complex dies all in the same package
Thanks to AI, TSMC has seen enormous demand for CoWoS. “Despite TSMC’s ongoing capacity expansion, CoWoS has remained in short supply since 2023, prompting customers to seek alternative capacity sources,” according to TrendForce.
“OSAT providers such as SPIL and Amkor have benefited from this spillover demand, and alternative technologies like EMIB and FOEB are also gaining traction, with Intel leveraging its U.S.-based manufacturing advantage,” according to TrendForce. Intel develops and sells a packaging technology called EMIB. FOEB is a form of fan-out wafer-level packaging.
TrendForce expects that the severe shortage in 2.5D packaging capacity will begin to ease slightly by 2027, aided by order spillover and TSMC’s plan to expand CoWoS capacity by over 60% by 2027.
Why won’t TSMC use high-NA EUV?
In 2018, TSMC became one of the first chipmakers to move into 7nm production. Then, in 2019, TSMC released a new version of 7nm. That process, dubbed N7+, represented TSMC’s first use of extreme ultraviolet (EUV) lithography.
EUV lithography is used to process the world’s most advanced chips. ASML, a Dutch-based company, is the sole supplier of EUV systems in the market. Generating light with a wavelength of 13.5nm, ASML’s EUV systems incorporate a 0.33 numerical aperture (NA) lens with 13nm resolutions. The 0.33 NA system is called low-NA EUV.
Since 2019, TSMC has released new and more advanced processes. 2nm is the company’s most advanced process. For the 2nm node, the foundry giant continues to use ASML’s 0.33 NA EUV tools.
As reported, TSMC recently released its latest technology roadmap. The company’s new process roadmap extends out to 2029. It announced several new processes, including A13, a 1.3nm technology, which is due out in 2029.
Making chips at the A13 process node is expected to be an expensive and difficult endeavor. So, at first glance, it makes sense to use ASML’s next-generation EUV lithography tools. ASML’s next-gen technology, called high-numerical aperture (high-NA) EUV, incorporates a 0.55 NA lens, enabling 8nm resolutions. ASML is shipping high-NA EUV tools in the market for R&D purposes.
However, TSMC has no plans to use high-NA EUV for the foreseeable future, including for the A13 node. From the 2nm node today to A13 in 2029, TSMC will continue to use 0.33 NA EUV lithography.
Why won’t TSMC use high-NA EUV for A13? Here’s four possible reasons:
1—TSMC and other chipmakers tend to extend their existing production equipment as long as possible. In other words, chipmakers (i.e. Intel, Samsung, TSMC, others) will extend 0.33 NA EUV as long as possible. At each new process generation, chipmakers will attempt to image smaller features, while also driving down the costs.
Basically, TSMC believes that it can extend 0.33 NA EUV to its A13 process in 2029. Then, when 0.33 NA EUV runs out of steam, TSMC will look at other options.
2—High-NA EUV is too expensive. At a starting point, a 0.33 NA EUV lithography tool sells for $180 million—each. In contrast, a high-NA lithography tool sells for a staggering $400 million each. Enough said.
3—The wrong tool at the wrong time? ASML’s high-NA tool is an engineering marvel. The system incorporates a new anamorphic lens technology. When printing images on a wafer, the anamorphic lens demagnifies the images by 4x in one direction and 8x in the other.
Thus, with the anamorphic lens, the exposure field is half the size, as compared to 0.33 EUV. High-NA EUV lithography is optimized to image tiny features on smaller dies.
There’s just one problem: Today’s AI chips are larger dies. To create a larger die, the images are printed on two masks and then stitched together. This methodology, called stitching, is a complex and expensive process. Many lithographers dislike the stitching process.
TSMC’s foundry customers include AMD, Nvidia and others. These companies are developing and selling AI devices, which are large chips.
With high-NA EUV, TSMC faces a higher cost-of-ownership, plus the dreaded stitching process. Low NA EUV is capable of processing current and future AI chips. So why bother with high-NA?
4—In the future, TSMC may consider high-NA, possibly in the next decade. That’s not a given. ASML is also working on a future technology called hyper-NA EUV, which could cost $1 billion for each tool.
Then, the Blue-X Technical Working Group (TWG) is exploring 3.1nm wavelength lithography to extend Moore’s Law. Others are also working on X-ray lithography. It’s all up in the air at this point.
New interposer supplier
VisionPower Semiconductor Manufacturing Co. (VSMC), a new fab venture in Singapore, plans to manufacture interposers for advanced packaging, according to a report from the Taipei Times. Under the plan, VSMC will obtain interposer technology from TSMC.
VSMC is a 300mm fab venture between Taiwan foundry vendor Vanguard International Semiconductor (VIS) and Dutch-based chip supplier NXP. VIS has a 60% stake in the venture, while NXP has 40%. Meanwhile, TSMC has a 27.55% stake in VIS.
Announced in 2024, VSMC is expected to manufacture mixed-signal, power management and analog chips.
Now, VSMC is expanding its portfolio. VIS will license TSMC’s interposer technology. VIS will transfer the technology to VSMC, which will make 30nm and 40nm interposers for advanced packaging, according to the Taipei Times.
VSMC will move into initial production in 2027.
India’s new GaN fab and packaging plant
The Indian government has approved two new semiconductor projects under the India Semiconductor Mission (ISM) initiative. The two projects include India’s first commercial Mini/Micro-LED display facility based on gallium nitride (GaN) technology and a semiconductor packaging facility. The plan is to turn these projects into new companies.
The two approved proposals will set up semiconductor manufacturing facilities in Gujarat with a cumulative investment of Rs. 3,936 crore (US$467.7 million). The total number of approved projects under ISM is now up to 12, with cumulative investments of Rs.1.64 lakh crore (US$19.48 billion.)
The first new project, called Crystal Matrix Ltd. (CML), will establish an integrated facility for compound semiconductor fabrication in Dholera, Gujarat for manufacturing Mini/Micro-LED display modules. The integrated facility will also provide GaN foundry services, including epitaxy on 6-inch wafers. The annual proposed production capacity for Mini/Micro-LED display panels is 72,000 square meters, and for Mini-Micro-LED GaN epitaxy wafers is 24,000 sets of RGB wafers.
The second new project, called Suchi Semicon Pte. Ltd. (SSPL), will set up an outsourced semiconductor assembly and test (OSAT) facility in Surat, Gujarat for manufacturing discrete semiconductor packages.
GaN wars
GaN is a hot—and competitive—market. In terms of market share, China’s Innoscience is the leader in the GaN device market with 30% share in the 2023/2024 timeframe, followed in order by U.S.-based Navitas (17%), U.S.-based Power Integrations (15.2%), U.S.-based EPC (13.5%), Germany’s Infineon (11.2%) and others, according to the Yole Group. Renesas, TI and others compete in the GaN market.
Two major players, Infineon and Innoscience, have been embroiled in a legal battle in the GaN device market. This week, there was a new legal ruling. Both companies claimed victory, creating some confusion in the market.
On May 7, Infineon issued the follow release: “The Full Commission of the U.S. International Trade Commission (ITC) affirmed the ITC’s initial determination from December 2025 that Innoscience infringed an Infineon patent concerning gallium nitride (GaN) technology and ordered import and sales bans against Innoscience. The ITC Commission’s final decision and the bans are subject to a 60-day review period of the US President.”
In a parallel dispute in Germany, Infineon is asserting infringement of three patents and one utility model in the Munich District Court I (Landgericht München I). Already in August 2025, the Munich court found infringement of the first Infineon patent by Innoscience. Trials for another patent and a utility model are scheduled in June 2026.
Then, on May 8, Innoscience announced that the U.S. ITC issued a Final Determination in Investigation No. 337‑TA‑1414 confirming that Innoscience’s current gallium nitride power devices do not infringe Infineon’s patents and may continue to be imported and sold in the United States without restriction.
“The Full Commission affirmed the Administrative Law Judge’s finding of no violation of U.S. Patent No. 9,070,755 and confirmed that Innoscience’s redesigned products—now embodied in its current commercial offerings—fall outside the scope of U.S. Patent No. 9,899,481. The Commission also invalidated four additional claims of the ’481 patent,” according to Innoscience.
Only two claims of the ’481 patent were found valid and infringed, and only with respect to legacy products that are no longer manufactured or sold. As a result, the associated import ban has no practical impact on Innoscience’s U.S. business. Innoscience will continue supplying its existing GaN power products to U.S. and worldwide customers uninterrupted.
Innoscience has also successfully pervaded the U.S. Patent and Trademark Office to initiate review of the remaining two claims and is confident they will likewise be invalidated.
Q1 chip sales
Thanks to AI, the semiconductor market is on record pace in terms of sales. The European Semiconductor Industry Association (ESIA) reports that, in the first quarter of 2026, the global semiconductor market recorded a sharp increase of 79.2% year-on-year, reaching US$298.55 billion in sales. All figures are based on the latest report from the World Semiconductor Trade Statistics (WSTS) organization.
“The global market expansion in Q1 2026 was primarily driven by MOS memory (+236.4%), logic (+40.1%), MOS micro (+18.8%), and analog (+14.9%) chips supported by rising demand from data centers and AI applications, cloud computing, and automotive applications,” according to ESIA.