Fraunhofer Forms Chiplet R&D Center For Automotive
German R&D organization launches a new R&D center to propel the development of chiplets.
By Mark LaPedus
Fraunhofer, a German R&D organization, has launched a new R&D center to propel the development of chiplets for the automotive industry.
The Dresden-based research initiative, called the Chiplet Center of Excellence (CCoE), will focus on the development of an automotive ecosystem for chiplets, including design methodologies, workflows, and demonstration vehicles.
Chiplets are becoming an important part of the semiconductor industry. Today’s AI chips, processors and other high-performance devices are fast and highly-integrated devices. These chips are also relatively large, and are difficult and expensive to manufacture in the fab.
One way to solve these problems is to embrace the chiplets concept. In chiplets, the idea is to break up a large device into smaller dies. Then, the dies are assembled in an advanced package. A package is a product that encapsulates a chip, protecting it from harsh operating conditions.
© Fraunhofer IIS/EAS
Electronics solutions based on chiplets are the first to allow the integration of various functional units in different technologies on a substrate or into a 3D chip structure.
The idea behind chiplets is to improve the yields and reduce costs. AMD, Apple, Intel, Nvidia and others have developed chips using the chiplet concept.
But there are challenges in developing a chiplet-based device. In chiplets, each die in the package must have few, if any, defects. Unwanted defects in a die could cause the entire chiplet-based product to fail.
Each die in the chiplet package must communicate with one another. Typically, for their respective chiplet-based designs, semiconductor vendors tend to use proprietary die-to-die communication protocols and interfaces. Larger semiconductor companies can afford to develop these technologies. Most vendors don’t have the resources.
Fortunately, the semiconductor industry is developing standard die-to-die technologies and protocols for chiplets. The idea is to allow more companies to adopt the chiplets concept using open standards.
In 2022, several companies banded together and announced the Universal Chiplet Interconnect Express (UCIe) Consortium. At the time, the consortium announced the new UCIe 1.0 specification. This specification covers a standard die-to-die I/O physical layer, die-to-die protocols, and software stacks.
In August 2024, the consortium announced the release of its 2.0 specification. This spec addresses the design challenges for testability, manageability, and debug for the lifecycle across multiple chiplets – from sort to management in the field. Additionally, the 2.0 specification supports 3D packaging.
More challenges
Fraunhofer, meanwhile, is addressing other challenges in the chiplets arena. “Using chiplets from different sources for product groups with smaller and medium batch sizes, such as for automotive applications, has thus far proved largely unviable,” according to the R&D organization.
For the first two years, the CCoE will focus on the automotive sector. The group hopes to bring together a range of partners all along the value chain–from car manufacturers to semiconductor companies.
The CCoE hopes to provide these companies with methodological approaches, architectural concepts, reusable basic components, and roadmaps for the development, manufacture, and robust design of chiplets.
The CCoE is operated by the Dresden-based Engineering of Adaptive Systems EAS division of the Fraunhofer Institute for Integrated Circuits IIS, the Fraunhofer Institute for Reliability and Microintegration IZM and its division All Silicon System Integration Dresden, as well as the Fraunhofer Institute for Electronic Nano Systems ENAS.
Companies interested in participating in the CCoE’s pre-competitive activities and shaping its research agenda have until fall 2024 to sign up here.
“Chiplets will play a critical role in the global semiconductor industry in the years ahead because this technology offers the greatest freedom possible for customizing the design of electronics systems. This makes it all the more important for European industry to have a coordinated roadmap for the incorporation of chiplets into its own products,” said Andy Heinig, department head at Fraunhofer IIS/EAS and head of the Chiplet Center of Excellence (CCoE). “That’s why it’s essential for companies to be able to assess the feasibility of chiplet-based system solutions early on. For this reason, at the CCoE we take the wide range of requirements and constraints these products have and convert them into practical workflows and new evaluation processes.”