Leti, Quobly Describe New FD-SOI Devices

At IEDM, researchers described FeRAMs, FeFETs and quantum computing devices using FD-SOI.

By Mark LaPedus

At the recent 2024 IEEE International Electron Devices Meeting (IEDM) in San Francisco, CEA-Leti, Quobly and others presented papers on various devices based on fully depleted silicon-on-insulator (FD-SOI) technology.

In one paper, CEA-Leti disclosed an embedded ferroelectric RAM (FeRAM) technology based on a 22nm FD-SOI process. The French R&D organization and others are also working on FD-SOI processes at the 10nm and 7nm nodes. In general, FD-SOI is a process that enables low-power chips.

In addition, several entities presented a paper on a related technology called the ferroelectric FET (FeFET) based on FD-SOI. And startup Quobly reported that FD-SOI technology can serve as a scalable platform for commercial quantum computing.

What is FD-SOI?

FD-SOI is not new. For years, several companies have been shipping low-power chips based on FD-SOI processes. This technology is ideal for embedded memory, microcontrollers (MCUs), wireless devices and other products.

In the FD-SOI process flow, a company first designs a chip. Then, the company decides which foundry vendor will manufacture the given chip line.

There are several foundry options here. GlobalFoundries offers a 22nm FD-SOI manufacturing process. Samsung Foundry provides 28nm and 18nm FD-SOI processes. STMicroelectronics provides foundry services as well as producing its own devices using a 28nm FD-SOI process.

Then, in R&D, Leti is developing next-generation FD-SOI processes, which will extend to the 10nm and 7nm nodes.

Meanwhile, in the manufacturing flow, a foundry vendor obtains a specialized FD-SOI substrate, or wafer, from Soitec or another supplier. Then, a foundry vendor manufactures a chip line using the FD-SOI substrate.

FD-SOI technology enables various chip types, which incorporates a traditional planar transistor structure. A transistor consists of a source and a drain structure on each end of a substrate. A gate structure resides in the middle. In operation, a gate voltage establishes a field. This allows or blocks a current flow between the source and drain.

In the FD-SOI transistor structure, the base material is silicon. Then, an ultra-thin layer of an insulator material, called a buried oxide, is situated on top of the base silicon. The buried oxide resides just below the source and drain.

In FD-SOI, there is no need to dope the channel, thereby making the transistor fully depleted, according to STMicroelectronics. Plus, the buried oxide layer helps reduce the leakage current and parasitic capacitance in chips.

In the marketplace, FD-SOI processes compete against 22nm and 28nm “bulk” processes from TSMC, UMC and others. The bulk wafers used by TSMC, UMC and others are less expensive than FD-SOI substrates.

But FD-SOI has some advantages over the bulk wafer processes at the 28nm and 22nm nodes. “FD-SOI has numerous other unique advantages, including back bias ability, very good transistor matching, near threshold supply capability, ultra-low sensitivity to radiation and very high intrinsic transistor speed, which allows it to handle mmWave frequencies,” said Christophe Maleville, chief technology officer and senior vice president of innovation at Soitec, in a paper at IEDM.

The apps

FD-SOI is also ideal for new and emerging embedded memory applications. At IEDM, CEA-Leti presented a paper on an embedded FeRAM platform based on 22nm FD-SOI technology.

Still in R&D, the FeRAM is a next-generation ferroelectric memory device. FeRAMs are not to be confused with ferroelectric RAMs (FRAMs). Commercialized in the 1990s, FRAMs are an older ferroelectric memory type used for niche applications. FRAMs use perovskite materials, which are not CMOS compatible. They cannot scale beyond the 130nm node.

FeRAMs are different than the older FRAMs. First, FeRAMs are compatible with CMOS. Second, they can scale far beyond the 130nm node. And they are fast and non-volatile with low power and high endurance. A non-volatile memory retains stored data even when a system is shut off.

If the industry can put FeRAMs into production, these devices could come in two forms—standalone chips and embedded memory. In embedded memory, the idea is that you embed a tiny memory block in a chip like an MCU.

CEA-Leti has demonstrated an embedded FeRAM platform. More specifically, the R&D organization has demonstrated a scalable hafnia-zirconia-based ferroelectric capacitor platform for embedded applications. A ferroelectric capacitor is like a traditional capacitor, but it consists of ferroelectric materials.

CEA-Leti’s ferroelectric capacitor technology opens the door for faster and energy-efficient memory solutions. The institute plans to demonstrate embedded Mbit memory arrays. These devices operate at voltages around 1V with high access rates.

“FD-SOI technology is well-known for its low-power capability and makes it a very good fit with FeRAM, which is intrinsically the most energy efficient memory technology at the bitcell level,” explained Simon Martin and Laurent Grenouillet of CEA-Leti. “Scaling down to 22nm required fabricating functional 2D ferroelectric capacitors down to 0.0028µm², as well as 3D ferroelectric capacitors, while keeping a relatively low thermal budget for HZO film crystallization.”

Meanwhile, in a separate paper at IEDM, the team of University of Notre Dame, Pennsylvania State University, EMD, GlobalFoundries, IBM, MIT Lincoln Laboratory, and the National University of Singapore presented a paper on FeFETs using FD-SOI.

FeFETs and FeRAMs are related. In FeFETs, hafnium oxide (HfO2) ferroelectric materials are integrated in the gate stack of a logic transistor. As a result, the logic transistor is transformed into non-volatile FeFET memory transistor.

In the IEDM paper, researchers are looking at ways to improve the switching speeds of the FeFET. “In this work, we performed a comprehensive combined experimental and modeling study on the polarization reset mechanisms of floating body (i.e., channel) ferroelectric FETs, an important class of devices with growing interest due to added functionalities and improved reliabilities,” said Zhouhang Jiang from the University of Notre Dame and the lead author of the paper.

Meanwhile, at IEDM, Quobly and others presented a paper on quantum computing. Quobly is developing silicon spin qubit devices based on STMicroelectronics’ 28nm FD-SOI process. Over time, Quobly is targeting a 100-qubit system with proof of scalability beyond 100,000 physical qubits.

Quantum computing is different than today’s computers. Today’s systems incorporate traditional processors and memory chips. The data is stored using a binary format (1s or 0s). In quantum computing, the data is stored in a device called a qubit. “A qubit can behave like a bit and store either a zero or a one, but it can also be a weighted combination of zero and one at the same time,” according to IBM in a blog.

In theory, quantum computers are faster than today’s computers. But quantum computing is still in the early stages of development. Quantum computers are still in R&D and are useful to a small degree.

At IEDM, Quobly addressed the critical challenges for scaling quantum systems. With CEA-Leti, CEA-IRIG and CNRS, Quobly demonstrated the key building blocks for a quantum computer leveraging commercial FD-SOI. The key achievements include:

*Cryogenic control electronics: Voltage gain up to 75dB, noise levels of 10-11V²∙μm²/Hz, and threshold voltage variability of 1.29mV∙μm.

*Ambipolar spin qubits: Co-integration of hole and electron qubits on FD-SOI technology, achieving 1μs manipulation speed for holes and 40μs coherence time (Hahn echo) for electrons.

*A two-qubit gate standard cell: Demonstration of double quantum dot operations with commercial FD-SOI.

Other papers

In a separate IEDM paper, CEA-Leti disclosed a device able to sense light and modulate it. This solid-state device integrates a liquid crystal-based spatial light modulator with a custom lock-in CMOS image sensor.

The integrated phase modulator and sensor embeds a 58- × 60-pixel array, where each pixel both senses and modulates light phases. The compact system provides intrinsic optical alignment, facilitating the use of digital optical phase conjugation techniques in applications such as microscopy and medical imaging.

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