Taiwan’s Powertech Expands Panel-Level Packaging Capacity
The company has purchased a factory from another Taiwan firm
By Mark LaPedus
In a move to expand its packaging capacity, Taiwan’s Powertech Technology (PTI) has purchased a factory from AOU for NT$6.898 billion (US$221.27 million).
AOU’s plant is located in the Hsinchu Science Park in Taiwan. Based in Taiwan, AOU is a producer and supplier of flat-panel displays.
PTI, the world’s fifth largest OSAT, plans to use the plant to expand its advanced packaging process manufacturing capacity and meet the growing demand for its fan-out panel-level package technology.
Outsourced semiconductor assembly and test (OSAT) vendors are an important part of the semiconductor industry. OSATs provide third-party packaging and testing services for the semiconductor industry.
Who is PTI?
Founded in 1997, Powertech Technology is the parent company of the PTI Group in Taiwan. The PTI Group includes Greatek Electronics, TeraPower and Tera Probe. In total, the PTI Group has over 18,000 employees with manufacturing facilities located in Taiwan, Japan and elsewhere.
Greatek provides a range of mature package types for customers. It also provides test services. TeraPower provides wafer testing services for memory and logic products. Based in Japan, Tera Probe provides wafer testing and final test services.
Powertech Technology, or PTI, provides a range of advanced package types for customers, including antennae-in-package (AiP), bumping, flip-chip and through-silicon vias (TSVs).
PTI’s specialty is panel-level fan-out. For this technology, PTI is expanding to meet demand. In 2025, PTI’s capital spending is expected to reach NT$19 billion (US$609.52 million), according to a report from the Taipei Times. In 2026, the company plans to more than double its capital expenditures to NT$40 billion (US$1.31 billion), according to the report. The funds will be used to expand its panel-level technology.
Panel-level packaging (PLP) is a different way to manufacture advanced packages. Typically, in some advanced package types, multiple chips are processed and packaged on round 200mm or 300mm wafers. In PLP, though, multiple chips are packaged on a large rectangular substrate or a panel. PLP allows for more chips to be processed at the same time, thereby increasing the throughput. PLP also reduces manufacturing costs.
PLP isn’t new. For some time, ASE, PTI, Samsung, STMicroelectronics and others have been making packages using PLP. TSMC is expected to enter the PLP field. In addition, Amkor, Innolux, ECHINT, Rapidus and Silicon Box have started developing PLP technology for large, high-end fan-out packaging, according to the Yole Group, a research firm.
In 2024, the total PLP market achieved about $160 million of revenue and a global production of almost 80 thousand panels (~330 thousand equivalent 300mm wafers), according to Yole. By 2030, this market could reach more than $650 million and a volume of approximately 220 thousand panels, according to Yole.
“Despite its benefits, PLP also comes with some hurdles, both from the economic and technical perspectives,” according to the research firm. “Large investments are needed to develop panel lines, and that investment is justified only for high-volume applications.”