The Latest News In IC Packaging & Test

Updated: What is EV Group planning at ECTC?; Nvidia's U.S. plans; AMD and Lisa Su; Altera; Applied takes stake in Besi; silicon photonic groups; ASE's best suppliers

By Mark LaPedus

IC packaging is an important part of the semiconductor industry.

Packaging is also a complex business with a multitude of facets. Plus, there is frenetic wave of new announcements in packaging. It’s hard to keep up with the announcements.

Test is also important. To help the industry, Semiecosystem has compiled the latest and more significant company and technology announcements in packaging and test. These announcements are listed in descending chronological order (see below). We will update the list throughout the year. (Send me an e-mail if I miss an announcement.)

EV Group

EV Group announced that new developments in heterogeneous integration enabled by its wafer-to-wafer and die-to-wafer hybrid bonding, maskless lithography, metrology and infrared (IR) laser release solutions will be highlighted in multiple papers being presented later this month at the 2025 IEEE 75^th Electronic Components and Technology Conference (ECTC), to be held May 27-30 in Dallas, Texas.

Menta

Menta SAS, a provider of embedded FPGA (eFPGA) IP, announced that Japanese technology company Secafy has licensed Menta's eFPGA IP to integrate into its upcoming chiplet-based products. The move supports Secafy's mission to develop highly secure and adaptable semiconductor solutions for next-generation applications.

Nvidia’s U.S. manufacturing plans

Nvidia is working with its manufacturing partners to design and build factories that, for the first time, will produce the company’s AI supercomputers entirely in the U.S.

The company has commissioned more than a million square feet of manufacturing space to build and test Nvidia’s Blackwell chips in Arizona and AI supercomputers in Texas.

The company’s Blackwell chips have started production at TSMC’s chip plants in Phoenix, Ariz. Nvidia is building supercomputer manufacturing plants in Texas, with Foxconn in Houston and with Wistron in Dallas. Mass production at both plants is expected to ramp up in the next 12-15 months.

Nvidia is partnering with Amkor and SPIL for packaging and testing operations in Arizona.

AMD’s 2nm HPC plans, Lisa Su

AMD has announced that its next-generation EPYC processor, codenamed “Venice,” is the first high-performance computing (HPC) product in the industry to be taped out and brought up on TSMC’s advanced 2nm (N2) process technology.

AMD also announced the successful bring up and validation of its 5th Gen AMD EPYC CPU products at TSMC’s new fabrication facility in Arizona, underscoring its commitment to U.S. manufacturing.

Separately, Lisa Su, chief executive of AMD, returned to her roots in Taiwan for an inspiring and wide-ranging discussion. TechSoda wrote a great piece on what Su said.

Altera’s fate

Intel has entered into a definitive agreement to sell 51% of its Altera business to Silver Lake, a private equity firm.

Intel will own the remaining 49% of Altera. The transaction, which values Altera at $8.75 billion, establishes Altera’s operational independence and makes it the largest pure-play FPGA (field programmable gate array) semiconductor company. Intel also announced that Raghib Hussain will succeed Sandra Rivera as chief executive of Altera, effective May 5. Hussain joins Altera from his previous role as president of Products and Technologies at Marvell.

Applied takes stake in Besi

Applied Materials has purchased 9% of the outstanding shares of the common stock of BE Semiconductor Industries (Besi), a manufacturer of assembly equipment for the semiconductor industry.

Applied and Besi have been collaborating since 2020, and recently extended their agreement, to co-develop the industry’s first integrated equipment solution for die-based hybrid bonding. Hybrid bonding is becoming a critical technology for advanced packaging. Hybrid bonding connects chips using direct copper-to-copper bonds, which increases density and shortens the lengths of interconnect wiring between chiplets, resulting in improved overall performance, power consumption and cost.

“We view this as a strategic, long-term investment that demonstrates Applied Materials’ commitment to co-developing the industry’s most capable hybrid bonding solution, a technology that is becoming increasingly important to the advanced logic and memory chips at the foundation of AI,” said Terry Lee, corporate vice president and general manager of heterogeneous integration and packaging at Applied Materials. “We look forward to furthering our collaboration with Besi and delivering innovative technology to our customers.”

Applied Materials and Besi have co-developed an integrated hybrid bonding system, which has the full capabilities chipmakers need to take the technology to very high-volume manufacturing over the next several years. The system brings together Applied’s expertise in front-end wafer and chip processing with high levels of bonding accuracy and speed from Besi’s leading die placement, interconnect and assembly solutions.

The investment was made through market-based transactions and is not subject to regulatory approvals. Applied does not intend to seek board representation at Besi, nor does it have plans to purchase additional shares of Besi common stock.

Separately, Applied recently introduced a new defect review system to help leading semiconductor manufacturers continue pushing the limits of chip scaling. The company’s SEMVision H20 system combines the industry’s most sensitive electron beam (e-beam) technology with advanced AI image recognition to enable better and faster analysis of buried nanoscale defects in the world’s most advanced chips.

Applied’s new e-beam technology is critical for complex 3D architecture inflections required to manufacture logic chips at the 2nm node and beyond – including new gate-all-around (GAA) transistors – as well as the formation of higher-density DRAM and 3D NAND memories. Applied’s SEMVision H20 defect review system has been adopted by leading logic and memory chipmakers for emerging technology nodes.

Silicon photonics special interest groups

The SEMI Silicon Photonics Industry Alliance (SiPhIA) officially launched three Special Interest Groups (SIGs) aimed at integrating expertise from various sectors to formulate industry standards and accelerate the commercialization of silicon photonics.

SEMI established the SiPhIA in 2024 to advance silicon photonics technology. K.C. Hsu, vice president of TSMC, and C.P. Hung, vice president of ASE, are the co-chairs of SEMI SiPhIA.

“Silicon photonics has become a key technology driving the development of artificial intelligence (AI) due to its advantages in high-speed data transmission, high bandwidth, low power consumption, and high integration,” according to SEMI. “However, it still faces challenges in manufacturing processes, packaging and testing to meet the rapidly increasing demand for data transmission. These challenges include shrinking chip sizes, reducing costs, minimizing energy loss in photonic integrated circuits, integrating photonic chips with advanced packaging, and developing effective solutions for heat dissipation.

To overcome these challenges, SEMI SiPhIA established three SIGs to accelerate breakthroughs and commercialization of silicon photonics technology. They include:

*SIG 1: System, Subsystems, and Silicon Photonics Technology Development, focusing on the future development trends in silicon photonics technology, including the design, manufacturing, and integration of silicon photonics chips, forming a complete silicon photonics ecosystem.

*SIG 2: Advanced Packaging and Testing, focusing on heterogeneous integration and co-packaged optical application packaging and testing technologies, driving optical-electronic integration.

*SIG 3: Equipment and Others, dedicated to developing and providing key equipment and technologies needed for the silicon photonics industry, focusing on process automation, including assembly, inspection technologies, and related equipment and innovative applications.

EU photonics hub

The European Union (EU) has invested €15 million in PhotonHub Europe.

Formed in 2021, PhotonHub Europe is a single pan-EU Photonics Innovation Hub, which integrates the best-in-class photonics technologies, facilities, expertise and experience of 53 partners from all over Europe.

This includes the coordinators of EU pilot lines and local photonics hubs, representing 18 regions, as a one-stop-shop solution offering a comprehensive range of support to the industry for the accelerated uptake and deployment of photonics. The hub is led by Brussels Photonics (B-PHOT) at Vrije Universiteit Brussel (VUB).

Hugo Thienpont, director of Brussels Photonics and coordinator of the PhotonHub program, said: “This €15M program funded by the European Commission will be instrumental in creating opportunities for collaborative innovation projects for wide-ranging sectors over the next four years, enhancing European sovereignty in this rapidly growing industry.”

ASE’s best suppliers

ASE recently held its “Best Suppliers of 2024” awards ceremony to recognize the critical contributions of its supply chain partners. This year, the event saw an increase in attendance with 450 representatives from over 140 suppliers supporting ASE, SPIL, and USI. Here are ASE’s best suppliers.

Chiplets hub

The Research Fab Microelectronics Germany (FMD) organization is helping to drive chiplet innovation through the APECS pilot line, which was launched at the end of 2024. Of the total of €730 million in funding allocated for APECS, a significant percentage will be dedicated to the technological development of chiplets.

To strengthen the industrial use of chiplets in Germany and across Europe, the FMD is now establishing the Chiplet Application Hub. The hub will serve as the operational framework for the APECS pilot line, ensuring that companies gain access to the latest chiplet advancements.

Student programs at ECTC

More than 2,000 scientists, engineers and businesspeople from more than 20 countries are expected to attend the 75th annual ECTC event, which will take place May 27-30, 2025 at the Gaylord Texan Resort & Convention Center in Dallas, along with 135+ exhibitors.

Now, the ECTC Executive Committee is announcing three new initiatives to complement its existing student-focused offerings. They are a Local Student Engagement Program, a Student Volunteer Service Program, and a Student Competition. These program aim to inspire students, enhance their participation, foster engagement, and provide valuable learning opportunities in the fast-growing field of microelectronics packaging.

3D co-packaged optics

Lightmatter has announced the Passage L200, the world’s first 3D co-packaged optics (CPO) product.

The L200 3D CPO family includes both 32Tbps and 64Tbps versions, representing a 5x to 10x improvement over existing solutions. This enables over 200Tbps of total I/O bandwidth per chip package, resulting in up to 8x faster training time for advanced AI models.

The Passage L200 3D CPO integrates the latest of Alphawave Semi’s chiplet technology portfolio, combining silicon-proven low power and low latency UCIe and optics-ready SerDes with Lightmatter’s photonic integrated circuit (PIC). Alphawave Semi’s advanced-node electrical integrated circuit (EIC) is 3D integrated on the Passage PIC using standard chip-on-wafer (CoW) techniques. Passage 3D integration enables SerDes I/O to be positioned anywhere on the die, rather than being confined to its shoreline, delivering the equivalent bandwidth of 40 pluggable optical transceivers per L200. Additionally, multiple L200s can be integrated in a package to serve a broad range of XPU and switch applications.

The L200 is engineered for high-volume manufacturing with industry leading silicon photonics fab and OSAT partners, including GlobalFoundries, ASE, and Amkor as well as advanced node CMOS foundries.

Lightmatter offers two product SKUs: the L200 (32Tbps) and L200X (64Tbps) 3D CPO engines. These solutions build upon the company’s Passage technology platform, offering 16 WDM wavelengths per waveguide/fiber with the most advanced and fully integrated photonics control capabilities.

3D photonics superchip

In a separate announcement, Lightmatter introduced the Passage M1000, a 3D photonic superchip designed for next-generation XPUs and switches.

The Passage M1000 enables 114Tbps of total optical bandwidth for the most demanding AI infrastructure applications. At more than 4,000-square-millimeters, the M1000 reference platform is a multi-reticle active photonic interposer that enables the world’s largest die complexes in a 3D package, providing connectivity to thousands of GPUs in a single domain.

In existing chip designs, interconnects for processors, memory, and I/O chiplets are bandwidth limited because electrical input/output (I/O) connections are restricted to the edges of these chips.

The Passage M1000 overcomes this limitation by unleashing electro-optical I/O anywhere on its surface for the die complex stacked on top. Pervasive interposer connectivity is enabled by an extensive and reconfigurable waveguide network that carries high-bandwidth WDM optical signals throughout the M1000. With fully integrated fiber attachment supporting 256 fibers, the M1000 delivers an order of magnitude higher bandwidth in a smaller package size compared to conventional co-packaged optics (CPO) and similar offerings.

Lightmatter has worked with industry leaders, including GlobalFoundries (GF) and Amkor, to facilitate production readiness for customer designs based on the M1000 reference platform. The Passage M1000 utilizes GF’s Fotonix silicon photonics platform.

ASE’s CPO device

Advanced Semiconductor Engineering (ASE) has demonstrated a co-packaged optics (CPO) device that mounts multiple optical engines (OE) directly onto a substrate, enabling <5pJ/bit power consumption and bandwidth increases.

ASE’s CPO solves the assembly challenge of multiple optical engines with an ASIC in an integrated package with a large body configuration of >75mm X 75mm. The benefits for both the networking and data center markets are significant. For networking, it provides a potential option to improve or replace pluggable optics at 1.6Tb/s or 3.2 Tb/s, as well as an integration solution that enables ultra-low latency option for CPO. For compute, the platform can be used to integrate the CPUs, GPUs, XPUs with the optics into a single co-packaged solution through high-speed optical data links.

ASE’s new configuration enables on-package energy efficiency and bandwidth expansion while addressing further data center challenges by delivering improvement related to latency, data throughput, and scalability.

UCIe chiplets

Ayar Labs has announced the industry’s first Universal Chiplet Interconnect Express (UCIe) optical interconnect chiplet.

By incorporating a UCIe electrical interface, this solution is designed to eliminate data bottlenecks and integrate easily into customer chip designs.

Capable of achieving 8Tbps bandwidth, the TeraPHY optical I/O chiplet is powered by Ayar Labs’ 16-wavelength SuperNova light source. The integration of a UCIe interface means this solution not only delivers high performance and efficiency but also enables interoperability among chiplets from different vendors. This compatibility with the UCIe standard creates a more accessible, cost-effective ecosystem, which streamlines the adoption of advanced optical technologies necessary for scaling AI workloads and overcoming the limitations of traditional copper interconnects.

Silicon photonics ATE

Teradyne has partnered with ficonTEC to announce the availability of the first high-volume, double-sided wafer probe test cell for silicon photonics.

This solution is designed to meet the growing demand for high-throughput electro-optical testing of silicon photonic wafers driven by co-packaged optics (CPO) applications.

The new test cell integrates Teradyne's UltraFLEXplus automated test equipment (ATE) and programming environment, IG-XL, with ficonTEC's advanced optical alignment, probing, and wafer handling technologies. This collaboration enables the testing of hybrid bonded PIC/EIC wafers in a production environment.

Moving to Foundry 2.0 and advanced packaging

At the upcoming SEMIEXPO Heartland conference, NHanced Semiconductors president Robert Patti will present on the critical role of advanced packaging in continuing the progress of Moore’s Law in semiconductor development.

According to Patti, transistor scaling alone no longer delivers meaningful benefits in economics, speed, and effective chip size. “In Gordon Moore’s seminal paper, he predicted a ‘Day of Reckoning’ for semiconductor scaling,” explained Patti. “That day has arrived. However, as predicted, there is another path forward for semiconductors to continue progress without relying solely on ever-shrinking devices. Advanced packaging is that new path, and it is at the heart of a new industry model known as Foundry 2.0.”

In his address, Patti will detail Foundry 2.0’s new path forward for the electronics industry – bringing together the best of all technologies and material solutions by using the interconnect and manufacturing methods typically used in building semiconductor devices themselves.

Thus, Foundry 2.0 sources best-of-class components from traditional foundries and combines them in novel and powerful assemblies. This foundry evolution, based on advanced packaging (AP), is inherently different from today’s traditional semiconductor foundry model. This radical shift expands the advanced packaging tool box to integrate heterogeneous components in 3D and 2.5D devices, leveraging application specific chiplets for cost reduction and innovation.

Patti, president and CEO of NHanced Semiconductors, recently sat down with Semiecosystem to discuss the future of Moore’s Law, advanced packaging, chiplets and Foundry 2.0.

SEMIEXPO Heartland, SEMI’s first Midwestern U.S. exposition to be held April 1-2 at the Indiana Convention Center in Indianapolis, will feature a conference program highlighting the latest developments in smart manufacturing and smart mobility

Heterogeneous photonics integration

X-FAB, SMART Photonics and Epiphany Design are collaborating to develop a new heterogeneous photonics integration platform. The platform combines indium phosphide (InP) chiplets, silicon-on-insulator (SOI) technology and Micro-Transfer-Printing (MTP). This in turn will enable high-speed, energy-efficient optical transceivers.

AI platform

Sarcina Technology has launched its AI platform to enable advanced AI packaging solutions that can be tailored to meet specific customer requirements. Leveraging ASE’s FOCoS-CL (Fan-Out Chip-on-Substrate-Chip Last) assembly technology, this platform includes an interposer, which supports chiplets using UCIe-A for die-to-die interconnects. This allows for the delivery of cost-effective and customizable advanced packaging solutions.

Nvidia’s co-packaged optics

Nvidia has rolled out a silicon photonics networking switch line using co-packaged optics. Nvidia’s silicon photonics ecosystem includes TSMC, Browave, Coherent, Corning, Fabrinet, Foxconn, Lumentum, SENKO, SPIL, Sumitomo Electric Industries and TFC Communication.

Packaging R&D center in Scotland

Scotland has obtained £9 million in funding to establish a new R&D center for the development of power electronics packaging technology.

The R&D center, to open in 2025, will be hosted by the National Manufacturing Institute Scotland (NMIS). Funded by Innovate UK, the R&D center is located at the University of Strathclyde’s Advanced Net Zero Innovation Center (ANZIC).

Austrian power electronics lab

Graz University of Technology (TU Graz) and Silicon Austria Labs (SAL) have launched a new joint power electronics research laboratory.

The lab, called PERL, is dedicated to advance the fundamental research for high frequency switched power converters. The research work aims to develop components based on wide bandgap (WBG) semiconductors, such as silicon carbide (SiC) and gallium nitride (GaN).

Researchers will study new power conversion topologies, the design of passive components, novel gate driving solutions, and smart packaging and integration techniques.

MRAM test acquisition

Sweden’s Mycronic has acquired Hprobe, a company headquartered in Grenoble, France, which has developed a technology for high-speed magnetic testing of MRAMs and magnetic sensors.

Founded in 2017, Hprobe has 14 employees. Net sales in 2024 amounted to EUR 4 million. “Mycronic has identified wafer and semiconductor tests as an attractive expansion area. Hprobe fits very well into this space with its unique technology, where a strong magnetic field is generated quickly over a large area. Hprobe has the potential of turning into a critical supplier for the MRAM test market. AI, VR, AR and the automotive industry all constitute emerging growth opportunities for Hprobe, and through their solutions, Mycronic can participate in this exciting development,” said Magnus Marthinsson, senior vice president of Global Technologies at Mycronic.

Hprobe will form a new business line within the Global Technologies division.

AOS’ MOSFET packages

Alpha and Omega Semiconductor (AOS) announced the release of two surface mounting package options for its MOSFET portfolio. The new GTPAK and GLPAK packages will first be available on AOS’ AOGT66909 and AOGL66901 MOSFETs, respectively. Combining MOSFET technology with advanced packaging, these devices provide low ohmic and high current capabilities, critical to reducing the number of parallel MOSFETs needed in high current designs such as in next-generation e-mobility and industrial applications.

Teradyne buys Quantifi

Teradyne has entered into a definitive agreement to acquire privately held Quantifi Photonics, a leader in photonic IC testing. This acquisition will enable Teradyne to deliver photonic integrated circuit (PIC) test solutions.

RISC-V-based chiplets program

The European Union (EU) has launched DARE, an initiative that will focus on high-performance computing and AI.

DARE, or Digital Autonomy with RISC-V in Europe, is developing cutting-edge chiplet processors—the essential building blocks for next-generation supercomputers. At the heart of the DARE project is the development of three RISC-V-based chiplets.

Supported by the EuroHPC Joint Undertaking, and coordinated by the Barcelona Supercomputing Center (BSC-CNS), the DARE program unites 38 partners from across Europe to develop next-generation processors and computing systems. The first phase of the budget consists of €240 million in funding.

Axelera AI obtains funding

Axelera AI has unveiled Titania, a high-performance and scalable AI inference chiplet. The development of this chiplet builds on Axelera AI’s approach to Digital In-Memory Computing (D-IMC) architecture, which provides near-linear scalability from the edge to the cloud.

To support this development, Axelera AI is receiving up to €61.6 million in funding from the EuroHPC Joint Undertaking (JU) and member states as part of the Digital Autonomy with RISC-V for Europe (DARE) Project. This new funding follows the close of an oversubscribed $68 million Series B financing round, bringing the total amount raised by Axelera AI to more than $200 million.

ATE deal

Advantest has entered into a partnership agreement with Micronics Japan Co. (MJC). Under this agreement, MJC and Advantest will leverage their respective expertise to provide semiconductor test solutions. Additionally, Advantest plans to acquire a minority stake in MJC as part of this agreement.

Chiplet standards

The Open Compute Project Foundation (OCP) and the JEDEC Solid State Technology Association have announced the availability of new chiplet design kits for use with today's EDA tools covering assembly, substrate, materials and test.

The design kits were developed in collaboration within the OCP Open Chiplet Economy Project. Leveraging the alliance between OCP and JEDEC, these design kits are now part of the Global World Wide Standard JEDEC JEP30: Part Model Guidelines.

"The new design kits, developed through collaboration between OCP and JEDEC, promote innovation in SiP design by fostering collaboration and openness, ensuring broad accessibility, and supporting rapid adoption across the semiconductor industry. These kits promote openness, streamline design workflows, and reduce manual interventions, thereby significantly improving design efficiency, scalability, and innovation," said James Wong, Palo Alto Electron, David Ratchkov, Thrace Systems and Michael Durkan, chair of the JEDEC JEP30 Task Group.

ECTC

More than 2,000 scientists, engineers and businesspeople are expected to attend the 75th annual IEEE Electronic Components and Technology Conference (ECTC) from May 27-30, 2025 at the Gaylord Texan Resort & Convention Center in Dallas.

ECTC is the premier international event bringing together the best in packaging, components, and microelectronic systems science, technology, and education in an environment of cooperation and technical exchange. Click here for more information.

Applied Materials

In a new blog, Applied Materials discussed various topics and challenges in advanced packaging.

To address the challenges, Applied Materials hosted a recent event. More than 30 industry experts tackled two key topics: technology challenges; and building talent and capacity. Here’s the link to the blog, and here's the key insights.

ASE

On Feb. 18, Taiwan’s ASE launched its fifth IC packaging plant in Penang, Maylasia.

The plant will build on the company’s packaging and testing capabilities in the Bayan Lepas Free Industrial Zone. The new plant is part of a strategic expansion plan that will expand the floor space of ASE’s Malaysia facility from its current area of 1 million square feet to 3.4 million square feet.

Over the years, the Malaysia site has been upgrading its manufacturing operations by integrating Industry 4.0 technology and factory automation solutions.

“Southeast Asia is increasingly becoming an important base for semiconductors, given its growing digital economy propelling the demand for advanced chips and its shift towards design and chip manufacturing in recent years. With Malaysia solidifying its position as a regional semiconductor hub, we see our expanded facility playing an even greater role across the global semiconductor value chain and contributing to the country’s economic growth,” said Tien Wu, COO of ASE. ASE also recently posted its results for quarter.

New packaging plants

Several companies have announced new packaging facilities. Some 13 new facilities have been announced by China- and Taiwan-based packaging houses alone, according to TrendForce on Jan. 31. Many are expected to ramp up in 2025. Which companies are building these new plants?

Oki

On Jan. 28, Japan’s Oki, in collaboration with Nisshinbo Micro Devices, announced that it has developed a 3D analog IC technology. This makes use of Oki’s Crystal Film Bonding (CFB) technology.

This technology enables 3D integration with legacy processes. Analog is ideal here. “Oki developed a new thin-film chiplet technology, consisting of lifting off and bonding (CFB process) followed by rewiring. It completely protects the analog IC's functionality and lifts off only the functional layer from the substrate. The thin-film analog IC is then bonded to another analog IC, enabling the successful 3D integration of thin-film analog ICs,” according to Oki.

For its part, Nisshinbo Micro Devices has developed a localized shielding technology. This technology shields only specific areas between upper and lower chips affected by interference, not the entire chip, suppressing signal interference without degrading circuit functionality.

PseudolithIC

On Jan. 27, PseudolithIC announced that it has raised $6 million in a seed funding round. The round was led by Entrada Ventures, with additional investments from Foothill Ventures and Uncork Capital.

PseudolithIC is a next-generation RF chipset company headquartered in Santa Barbara, Calif. The company specializes in developing high-performance RF solutions using a silicon platform supplemented with compound semiconductor chiplets. In 2025, PseudolithIC is releasing product samples for millimeter-wave power amplifiers, low-noise amplifiers and transmit/receive front-ends.

Jim Buckwalter, CTO of PseudolithIC and Professor of Electrical and Computer Engineering at UC Santa Barbara, said: “The hybrid approach of combining silicon and compound semiconductor chiplets unlocks new potential for RF systems, enabling faster data rates, lower latencies, and better reliability.”

Baya

On Jan. 23, Baya Systems, based in Santa Clara, Calif., announced that it raised $36+ million in a Series B round led by Maverick Silicon, backed by a strategic investment from Synopsys, with current investors including Matrix Partners and Intel Capital.

The funding will accelerate the development and deployment of the company’s software-driven system IP technology portfolio for system-on-chip (SoC) designs and the chiplet economy. 

“Baya’s performance-focused, software-based approach, coupled with our unique transport and modular fabric IP, is designed from the ground up to produce complex multi-die solutions that are correct by construction with a simplified design process,” said Sailesh Kumar, founder and chief executive of Baya Systems.

GlobalFoundries

On Jan. 17, GlobalFoundries (GF) announced plans to create a new center for advanced packaging and testing of U.S.-made chips within its New York manufacturing facility. GF also announced a new CEO.

Infineon

On Jan. 14, Infineon announced that it has broke ground on a new semiconductor backend production site in Samut Prakan, south of Bangkok, in Thailand. The new manufacturing site is designed to meet the growing demand for its power modules. The first building is planned to be ready for operations at the beginning of 2026.

2024 was a big year for Infineon in terms of new manufacturing innovations. Last year, Infineon reached a breakthrough in handling and processing the thinnest silicon power wafers ever manufactured, with a thickness of only 20 micrometers and a diameter of 300mm, in a semiconductor fab.

Halving the thickness of a wafer reduces the wafer’s substrate resistance by 50%, reducing power loss by more than 15% in power systems, compared to solutions based on conventional silicon wafers.

To overcome the technical hurdles in reducing wafer thickness to the order of 20 micrometers, Infineon devised a new wafer grinding approach, since the metal stack that holds the chip on the wafer is thicker than 20 micrometers.

The technology has been qualified and applied in Infineon’s Integrated Smart Power Stages (DC-DC converter), which have already been delivered to first customers.

In addition, Infineon last year developed the world’s first 300mm power gallium nitride (GaN) wafer technology. Jochen Hanebeck, CEO of Infineon, said: “The technological breakthrough will be an industry game-changer and enable us to unlock the full potential of gallium nitride.”

The breakthrough will help drive the market for GaN-based power semiconductors, but it’s unclear when the industry will migrate to 300mm GaN wafers.

200mm represents is the state-of-the-art for GaN wafers. “As of 2024, the power GaN industry is indeed transitioning significantly to 200mm, driven by several key players, such as Innoscience, Infineon, STMicroelectronics, Texas Instruments, TSMC, X-FAB, VIS, and many more. We expect 200mm to be the mainstream platform during the next five years,” said Ezgi Dogmus, an analyst at Yole Group. “High-volume production on 300mm will be driven by increased demand for GaN applications in several power electronics applications, as well as the availability of front-end tools."