Wafer Cleaning Challenges Grow For Chips, Chiplets

ACM Research discusses the importance and challenges of wafer cleaning tools for advanced chips, memory and packaging.

By Mark LaPedus

Jim Straus, vice president of sales at ACM Research, and Sally-Ann Henry, chief technologist at ACM Research, sat down with Semiecosystem to discuss the semiconductor industry as well as the wafer cleaning tool challenges for advanced chips, memory and chiplets. ACM Research is a supplier of wafer cleaning tools, deposition products, electrochemical plating (ECP) systems, and wafer track units.    

Semiecosystem: From your vantage point, what are some of the current and future growth drivers in the semiconductor industry?

Henry: Currently, I would say the major growth drivers within the semiconductor industry are AI, automotive and chiplets. We are witnessing rapid growth in demand for these three areas.

Straus: I would expand upon what Sally-Ann mentioned and add wafer-level packaging as that is enabling 'More Than Moore’ to the list. Other important critical drivers also include compound semiconductors enabling automotive and battery technology and AI-enabling technology.

Semiecosystem: ACM Research has a strong position in the wafer cleaning equipment market for semiconductor fabs. What is wafer cleaning and why do we need it in the semiconductor industry?

Henry: Wafer cleaning is the process of the removal of chemical and particle impurities without damaging the wafer surface or substrate. The surface of the wafer must not be affected by any roughness, corrosion or pitting as these defects can impact device performance.

Straus: For silicon wafers to function properly, it must be free from any unwanted particles or contaminants. However, getting rid of these defects is not a simple task, especially because silicon wafers are fragile. This is why it’s important for IC manufacturers to develop cleaning techniques that will provide clean wafer surfaces while preventing the risk of damage.

(ACM Research’s Ultra C Tahoe cleaning system for semiconductor fabs. In IC manufacturing, wafer-level packaging, and compound semiconductor device manufacturing, wafer cleaning systems are used for both removal and additive processes like wafer cleans, etch, photoresist strip, metal lift-off, coating, and developing. Source: Company)

Semiecosystem: Semiconductor manufacturers have used cleaning tools in the fab for several years. When chips were less complex many years ago, I assume the cleaning tools and cleans were relatively simple. Is that right? What types of cleaning tools were used during that period?

Henry: The process of cleaning wafers has evolved over time. While cleaning for large devices greater than 130nm in the 80s and 90s was similar, the specifications were much looser and manual wet benches were used. These were eventually replaced with automated wet benches and subsequently batch spray tools. Single-wafer wet clean was then introduced in the early 2000s, mainly for BEOL (backend-of-line) with the introduction of copper wiring. By 2010, advanced fabs were using single wafer tools for most FEOL (front-end-of-the-line) wet clean processes to improve performance and yield. Due to the key growth drivers mentioned before, we anticipate future cleaning technologies to continue to evolve.

Semiecosystem:  Over the last decade, we’ve seen some major innovations in the semiconductor industry. Starting in 2011, for example, the industry migrated from planar transistors to more advanced finFETs for high-performance chips. Now, we are hearing about next-generation gate-all-around (GAA) transistors at the 3nm/2nm nodes. At advanced nodes, chipmakers face several challenges to manufacture chips. What are some of the wafer cleaning issues and challenges at advanced logic nodes?

Henry: As these structures continue to shrink, the process technology becomes more challenging as removing contamination and random defects becomes extremely difficult. With minimum feature sizes and film thicknesses reaching the 10nm level (100 Ångstroms), a particle as small as 1nm (10Å) can be a killer defect causing a transistor not to function. Removing particles and other contaminants to reach acceptable yields in the manufacturing process will be one of the major process challenges for semiconductor manufacturers as chip features continue to shrink below 10nm.

Straus: Today’s systems are comprised of sophisticated process equipment that accurately measures cleaning chemistries and removes micro contamination and defects after etch, lithography, and chemical mechanical polishing. Conventional particle-removal cleaning is challenged by today’s advanced technologies’ smaller and finer features. The pressure levels administered when using a spray cleaning technology can be too strong to the point the physical force will damage the surface features of the transistor and capacitor structures, potentially knocking them off the wafer. It is also important for spray technology to not reach into trenches with deep aspect ratios or other complex structures as that can lead to damage.

Semiecosystem: At advanced nodes, do chipmakers require new and different cleaning tools in the fab? Any new chemistries or the same ones?

Henry: In advanced nodes, the use of single wafer cleaning is predominant using dilute standard RCA chemicals to prevent etching of the surface. The issue with drying the feature without creating watermarks or pattern collapse has involved the progression of using IPA, hot IPA, surface modification chemistry (SMT) and finally super critical CO2 (SCCO2).

Semiecosystem: In general, how many cleaning steps are involved in a typical advanced logic process?

Henry: In typical logic process, there are 200 to 300 cleaning steps.

Semiecosystem:  What about memory devices, such as DRAM and 3D NAND? Are there any wafer cleaning issues and challenges here?

Straus: The cleaning issues are mainly around the removal of small defects or cleaning the inside of a DRAM capacitor without leaving chemical, water and drying without collapse. The 3D NAND memory array has similar issues to the DRAM capacitor in cleaning and reaching the bottom of the ONO (oxide-nitride-oxide) structures without leaving chemical and water in the deep holes and for the pattern not to collapse. All of the above can be accomplished using ACM Research’s TEBO cleaning technology tool with SCCO2 dry.

Semiecosystem: Packaging is a hot topic. What are some of the issues for wafer cleans in advanced packaging and chiplets?

Henry: For advanced packaging, etching and cleaning of the chiplets is critical, as is removing flux without causing corrosion from chemicals and water. ACM Research’s Ultra C v Vacuum Cleaning Tool addresses the requirement of removing flux that is used after reflow as part of the advanced packaging process. As feature sizes of these devices continue to shrink, traditional cleaning under atmospheric pressure is no longer sufficient.

Straus: By developing a tool that can clean under vacuum, the surface wetting ability is improved for liquid to flow into very narrow spaces to fully remove flux residues within a reasonable cleaning time. For devices that require very high flux dipping, a saponification agent can be added to achieve a complete clean.

Semiecosystem: ACM Research sells different types of wafer cleaning tools. Can you explain more about your Ultra C Tahoe system including how it works and its performance capabilities?

Henry: The Ultra C Tahoe is a hybrid tool with the capability of running sulfuric peroxide mix (SPM) in tanks to save chemical usage and disposal cost versus running SPM in a single wafer tool. After the SPM process and DIW, the wafers are transferred wet in the same platform to single wafer chambers for final rinsing and cleaning with multiple chemicals to meet the tight defect specifications for advanced devices while saving up to 60% of SPM usage.

Semiecosystem: In recent times, ACM Research has expanded its efforts into several new equipment markets, such as electroplating, PECVD, wafer track and others. Generally, what’s the strategy here?

Henry: ACM Research wants to expand its portfolio outside of cleaning. We are leveraging our learnings from wet clean to create tools for other process steps. We have good market share in ECP and we are slowly growing the tool platforms such as PECVD and track.

Semiecosystem: Can you comment on your roadmap?

Straus: The roadmap for the next few years is to increase market share in logic, memory, advanced packaging and SiC/GaN devices with existing products and the introduction of new products for different processes. The expansion of our customer base outside of Asia will require differentiated and sustainable technology that we are creating today.