The Latest News In IC Packaging & Test
Update: SEMI's new board members; digital twins conference; Qualcomm buys Alphawave Semi; EU sustainability project; Micron’s 1γ (1-gamma) DRAM; Alphawave Semi’s IP; Soitec, Powerchip go 3D
By Mark LaPedus
IC packaging is an important part of the semiconductor industry.
Packaging is also a complex business with a multitude of facets. Plus, there is frenetic wave of new announcements in packaging. It’s hard to keep up with the announcements.
Test is also important. To help the industry, Semiecosystem has compiled the latest and more significant company and technology announcements in packaging and test. These announcements are listed in descending chronological order (see below). We will update the list throughout the year. (Send me an e-mail if I miss an announcement.)
SEMI elects ASE’s Wu as International Board Chair
SEMI, the industry association representing the global electronics design and manufacturing supply chain, announced that its international board of directors has elected Tien Wu, CEO of Advanced Semiconductor Engineering (ASE), as its new chair, and Benjamin Loh, chair of Comet AG, as its new vice chair, effective immediately, in accordance with the association's by-laws.
Wu and Loh will lead the SEMI International Board of Directors Executive Committee in evolving the association’s operations, programs and services worldwide to support industry growth and its member companies. Wu previously served as vice chair of the board, while Loh served as a board member.
Digital twins conference
The inaugural SMART USA Institute Summit will take place from June 26-27 in Arlington, Va.
The conference will address the future of digital twin research in semiconductor manufacturing. This event is an opportunity to collaborate with leaders in industry, government, and academia to forge the next wave of semiconductor innovation.
Click here for the details of the event.
The event is spearheaded by the Semiconductor Manufacturing and Advanced Research with Twins USA Institute (SMART USA). This group is at the forefront of America’s efforts to reclaim global leadership in semiconductor manufacturing through the power of digital twin technology.
As a Manufacturing USA institute funded under the CHIPS and Science Act, SMART USA brings together a national community of industry leaders, academic institutions, national laboratories, small businesses, and workforce organizations to solve critical challenges facing domestic semiconductor production.
Qualcomm buys Alphawave Semi
Qualcomm has acquired Alphawave Semi for approximately $2.4 billion.
The acquisition of Alphawave Semi aims to further accelerate, and provide key assets for, Qualcomm’s expansion into data centers. Qualcomm Oryon CPU and Hexagon NPU processors are positioned to meet the growing demand for high-performance, low-power computing, which is being driven by a rapid increase in AI inferencing and the transition to custom CPUs in data centers.
Alphawave Semi is a provider of high-speed wired connectivity and compute technologies delivering IP, custom silicon, connectivity products and chiplets.
Alphawave Semi’s products form a part of the core infrastructure enabling next generation services in a wide array of high growth applications, including data centers, AI, data networking and data storage.
EU sustainability project
A pan-European consortium dedicated to developing sustainable processes and technologies for the semiconductor manufacturing industry has announced the launch of the GENESIS project.
This integrated, large-scale initiative aims to enable Europe's chip industry to meet its sustainability goals—from materials development to final waste treatment.
Coordinated by CEA-Leti, the three-year project brings together 58 partners spanning the entire European semiconductor value chain, from large enterprises and SMEs to research institutes, universities, and industry associations. GENESIS will drive solutions in emission control, eco-friendly materials such as alternatives to PFAS-based ones, waste minimization, and raw material reuse, directly aligned with the European Green Deal and European Chips Act.
“GENESIS is designed to address the complex challenges of building a truly sustainable semiconductor ecosystem," said Laurent Pain, sustainable electronics program director at CEA-Leti. “Its structure reflects both the urgency and the opportunity of Europe's green transition, powered by the complementary expertise and close collaboration of its partners."
Pain, manager of the project, noted that the team expects to deliver approximately 45 sustainability-driven innovations covering the semiconductor lifecycle, guided by four strategic pillars that form the technological foundation of GENESIS's vision for a green European semiconductor industry:
Pillar 1 – Monitoring & Sensing: Real-time emissions tracking, traceability, and process feedback systems
Pillar 2 – New Materials: PFAS-free chemistries and low-GWP alternatives for advanced semiconductor processes
Pillar 3 – Waste Minimization: Innovations in recycling (solvent, gas, slurries), reuse, and sustainable replacements
Pillar 4 – Critical Raw Materials Mitigation: Strategies to reduce dependency on CRM and strengthen resource security
Micron’s 1γ (1-gamma) DRAM
Micron Technology is shipping qualification samples of the world’s first 1γ (1-gamma) node-based low-power double data rate 5X (LPDDR5X) DRAM, designed to accelerate AI applications on flagship smartphones. Delivering the industry’s fastest LPDDR5X speed grade of 10.7 gigabits per second (Gbps), combined with up to a 20% power savings, Micron LPDDR5X DRAM transforms smartphones with faster, smoother mobile experiences and longer battery life — even when executing data-intensive workloads such as AI-powered translation or image generation.
To meet the industry’s increasing demand for compact solutions for next-generation smartphone designs, Micron has shrunk the LPDDR5X package size to offer the industry’s thinnest package of 0.61 millimeters, making it 6% thinner compared to competitive offerings, and representing a 14% height reduction from the previous generation.
Micron’s 1γ-based LPDDR5X DRAM is the company’s first mobile solution to leverage EUV lithography. Micron is currently sampling 1γ-based LPDDR5X 16 gigabyte (GB) products to select partners and will offer a wide range of capacities from 8GB to 32GB for use in 2026 flagship smartphones.
Alphawave Semi’s IP
Alphawave Semi has announced the tape-out of one of the industry’s first UCIe IP subsystem on TSMC’s N2 process, supporting 36G die-to-die data rates. The solution is fully integrated with TSMC’s Chip-on-Wafer-on-Substrate (CoWoS) advanced packaging technology.
Alphawave Semi’s UCIe IP subsystem on TSMC’s 2nm process delivers 36G performance with 11.8 Tbps/mm bandwidth density, ultra-low power and latency, and advanced features like live per-lane health monitoring and comprehensive testability.
Soitec, Powerchip go 3D
Soitec has announced a strategic collaboration with Powerchip Semiconductor Manufacturing Corp. (PSMC), a Taiwan-based foundry vendor.
Under the collaboration, Soitec will supply PSMC with 300mm substrates incorporating a release layer, Transistor Layer Transfer (TLT) ready, to support a new demonstration of advanced 3D chip stacking at the wafer level. This marks the first public announcement of Soitec’s TLT technology.
The stacking process enables multiple transistor layers to be built vertically to support 3D transistor architectures including vertical field-effect transistors (FETs) with backside power delivery networks (PDNs).
This TLT substrate leverages Soitec’s Smart Cut technology together with infrared (IR) laser release processing. The proprietary Soitec technology enables the formation of an ultra-thin semiconductor layer, ranging from 5nm to 1µm in thickness, on top of the TLT substrate. Once devices are fabricated on the TLT wafer, the IR laser process facilitates the lift-off of the ultra-thin layer from the substrate to the target wafer, without introducing thermal stress or damaging the devices.
AMD buys photonics firm
AMD has acquired Enosemi, a provider of chiplets, custom silicon and IP products. “Now as part of AMD, the team will help us immediately scale our ability to support and develop a variety of photonics and co-packaged optics solutions across next-gen AI systems,” said Brian Amick, senior vice president of technology and engineering at AMD, in a blog posting. “The elite team of experts and PhD-level talent at Enosemi, based in Silicon Valley, has a proven track record of building and shipping photonic integrated circuits in volume, a unique feat that few select teams have accomplished.”
Marvell’s multi-die solution
Marvell Technology has expanded its packaging ecosystem for AI infrastructure with a multi-die solution that lowers total cost of ownership (TCO) for custom AI accelerator silicon.
The advanced packaging platform is part of Marvell’s IP portfolio for custom AI compute platforms—and enables multi-chip accelerator designs 2.8x larger than conventional single-die implementations.
The solution includes a modular RDL interposer. The Marvell approach can enable more efficient die-to-die interconnect, lower power consumption, increased chiplet yields and lower product cost, and provides a manufacturing alternative to traditional interposer-based multi-chip approaches.
The packaging platform has been qualified with a major hyperscaler and is now ramping in production.
EV Group’s litho tool
EV Group has introduced the LITHOSCALE XT maskless exposure system, a high-throughput/high-resolution digital lithography solution for heterogeneous integration applications.
With a new dual-stage design, up to six exposure units, a dual-wavelength direct laser source as well as additional hardware and software enhancements, the LITHOSCALE XT offers up to a five-fold increase in throughput compared to the company’s current-generation LITHOSCALE solution.
The LITHOSCALE XT is suited for applications involving multi-die patterning, fan-out wafer-level packaging (FoWLP) for AI and high-performance computing (HPC) devices, panel-level packaging, MEMS, advanced imaging sensors, and die traceability for security and automotive applications.
LITHOSCALE XT tackles legacy bottlenecks associated with steppers by combining digital processing that enables real-time data transfer and immediate exposure, with high structuring resolution and high throughput. Key features include:
*Up to six exposure heads to cover a 300-mm wafer or 300-mm x 300-mm panel substrate in a parallel exposure process
*High-resolution (down to sub-2-micron lines/spaces), stitch-free, full-wafer patterning with no field-exposure or die-size limitations
*Simple switching between mask layouts, supporting multi-die patterning without the associated high cost of ownership for having many masks
*Real-time wafer-level distortion and die-shift compensation for bowed or warped wafers, enabling improved die-placement accuracy and patterning yield without impact on throughput
*Supports a wide range of exposure applications thanks to a dual-wavelength laser source (e.g., thin and thick photoresists, <1 micron up to >100 microns in thickness, chemically amplified resists, positive and negative tone, dielectrics, high-aspect-ratio patterning, etc.)
IEEE Award
Promex Industries, Inc., a Silicon Valley-based provider of advanced design, packaging, and microelectronics assembly services, announced that CEO Richard (Dick) Otte has received the 2025 Electronics Manufacturing Technology Award from the IEEE Electronics Packaging Society (EPS). The annual award recognizes individuals who have made impactful, sustained contributions to the field over 15 years or more, such as leading the development of major new processes in electronic manufacturing or significantly improving the yield or reliability of established processes.
GF, A*STAR deal
GlobalFoundries has announced plans to expand its capabilities in advanced packaging through a new memorandum of understanding (MOU) signed with the Agency for Science, Technology and Research (A*STAR), Singapore’s lead public sector research and development (R&D) agency.
Under the MOU framework, A*STAR will provide GF with access to its R&D facilities, capabilities and technical support, while GF will provide critical equipment to A*STAR to further its R&D efforts.
New EU OSAT
Thales, Radiall and Foxconn have initiated preliminary discussions to explore the potential creation of a new outsourced semiconductor assembly and test (OSAT) venture.
This France-based initiative is expected to aggregate additional European industrial partners to sustain an investment in excess of €250 million and ensure a strong European leadership for the project.
ClassOne, IBM deal
ClassOne Technology has signed a joint development agreement with IBM Research focused on wet processing for advanced packaging. The two companies will leverage their respective semiconductor chemistry expertise to create solvent solutions for a range of advanced semiconductor and packaging process applications.
The focus of the joint project will be to develop best known methods (BKMs) for non-NMP solvent processing in manufacturing IBM semiconductor devices. NMP, or N-Methylpyrrolidone, is a chemical compound long used in a variety of industries, including semiconductor fabrication, for removal of surface materials.
Broadcom’s next-gen CPO
Broadcom has announced several new and major advancements in its co-packaged optics (CPO) technology with the launch of its third-generation 200G per lane (200G/lane) CPO product line.
In addition to the 200G/lane breakthrough, Broadcom also demonstrated the maturity of its second-generation 100G/lane CPO products and ecosystem, highlighting key improvements in OSAT processes, thermal designs, handling procedures, fiber routing, and overall yield. A growing list of publicly-announced industry partners further underscores Broadcom's CPO platform readiness, enabling AI scale-out and scale-up applications for large AI deployments.
With the announcement of the third-generation 200G/lane CPO product line, alongside commitment to developing a fourth-generation 400G/lane solution, Broadcom continues to lead the industry in delivering the lowest power and highest bandwidth density optical interconnects.
Broadcom’s advancements in CPO technology are supported by the growing number of publicly announced partnerships across the ecosystem, as several major collaborators announced significant milestones, including:
*Corning has announced a collaboration with Broadcom on advanced fiber and connector technology.
*Delta Electronics has announced the production for the TH5-Bailly 51.2T CPO Ethernet switch in a compact 3RU form factor, available in both air-cooled and liquid-cooled configurations.
*Foxconn Interconnect Technology has revealed the production release of CPO LGA sockets and Pluggable Laser Source (PLS) cages and connectors, critical components for ensuring reliable, high-performance system integration.
*Micas Networks announced the production of the TH5-Bailly network switch system that delivers more than 30% system level power savings compared to systems with traditional pluggable modules.
*Twinstar Technologies celebrated milestone volume shipments of high-density CPO fiber cables.
Micas rolls out CPO switch
Micas Networks recently announced the volume production of its 51.2T Co-Packaged Optics (CPO) switch system. Micas’ next-generation switch is developed with Broadcom.
CPO is an emerging and enabling technology. The relentless demands of AI and high-speed networking are rapidly pushing data centers beyond the capabilities of traditional copper interconnects. As data rates surge to 400Gbps and higher, copper's limitations become a critical bottleneck, hindering performance and scalability.
CPO overcomes these electrical constraints and enabling seamless optical scaling for next-generation infrastructure. CPO technology integrates the optical engine with the switch chip in a single package, eliminating pluggable optics and shortening electrical signal paths to improve efficiency.
This design reduces power consumption, simplifies thermal management, and enhances signal integrity. Benchmark testing on fully populated switches confirmed system power savings of more than 40% compared to systems populated with standard pluggable transceivers and more than 25% compared to systems populated with linear pluggable optical (LPO) transceivers.
Meanwhile, the new Micas CPO switch system features Broadcom’s 51.2T Bailly CPO switch device that includes its Tomahawk 5 switch chip directly coupled to and co-packaged with eight 6.4-Tbps Silicon Photonics Chiplets in Package (SCIP) optical engines.
Micas’ product also includes:
*4RU system design with high-efficiency air cooling to deliver 128 ports of 400G FR4 connectivity externally fiber coupled with 128 duplex LC optical connectors (sub-2RU systems achievable with MPO connectors)
*CPO engine to front-panel routing supports traditional fiber with creative fiber box solutions
*System design compatible to support multiple remote laser modules (RLM)
*More than 30% whole switch power consumption savings compared to standard pluggable optics solutions
“Micas is committed to delivering cost-effective, cutting-edge network solutions at scale,” said Charlie Hou, vice president of strategy for Micas Networks. “With our deep investment in R&D, in-house manufacturing, robust supply chain, and strategic partnership with Broadcom, we provide high-performance open network switches that support various operating systems, including SONiC.”
CEA-Leti’s LID World Summit
LID World Summit 2025, slated from June 17–19, will spotlight the foundational role of advanced semiconductors in unlocking the full potential of AI—from edge devices to data centers, and present innovative advances and ideas for key microelectronic sectors.
LID will also provide actionable insights for industrials, SMEs, and startups aiming to capitalize on the next wave of technological breakthroughs.
The LID World Summit is the cornerstone of CEA-Leti’s international events and its largest annual gathering. In its 27th year, it will bring together a global community of more than 1,100 industry leaders, researchers, academics, and innovation stakeholders to explore the future of microelectronics and deep tech. Click here for more information.
DRC conference
The 2025 Device Research Conference (DRC) marks its 83rd anniversary as the longest running device research meeting in the world, continuing to be premier international forum to present innovative semiconductor device research, including emerging technology trends such as memory devices, quantum devices, optoelectronics/photonics, and wide bandgap power devices, as well as serving as a platform to nurture the next generation of device engineers.
The 83rd annual DRC will be held from June 22-25, 2025 at Duke University in Durham, NC. Registration for the conference is now open. The complete conference program is available here.
EV Group
EV Group announced that new developments in heterogeneous integration enabled by its wafer-to-wafer and die-to-wafer hybrid bonding, maskless lithography, metrology and infrared (IR) laser release solutions will be highlighted in multiple papers being presented later this month at the 2025 IEEE 75th Electronic Components and Technology Conference (ECTC), to be held May 27-30 in Dallas, Texas.
Menta
Menta SAS, a provider of embedded FPGA (eFPGA) IP, announced that Japanese technology company Secafy has licensed Menta's eFPGA IP to integrate into its upcoming chiplet-based products. The move supports Secafy's mission to develop highly secure and adaptable semiconductor solutions for next-generation applications.
For more announcements in the packaging and test market, click here.